Welcome to uComputing Lab at KAIST!

Update
Conference paper accepted to GLSVLSI, 2017 (송영수, 정진욱)
"Redundant via insertion with cut optimization for self-aligned double patterning"
Conference paper accepted to DAC, 2017 (서재우, 정진욱)
"Pin accessibility-driven cell layout redesign and placement optimization"
Seongbo Shim receives Outstanding Ph.D. Dissertation Award Photo photos
Awarded by KAIST President to one Ph.D. graduate out of all graduates of EE department in year 2016
Internship at IMEC, Belgium, 2017.1 - 2017.2 (최수형)
Worked on optical-proximity-correction (OPC)
Conference paper accepted to ISQED, 2017 (현대준, Wachirawit Ponghiran)
"Clock tree optimization through selective airgap insertion"
Prof. Shin has been elevated to IEEE Fellow 2017
for contributions to design tools for low-power, high-speed VLSI circuits and systems
Journal paper accepted to IEEE Transactions on Semiconductor Manufacturing, 2017 (심성보)
"Machine learning-guided etch proximity correction"
Conference paper accepted to DATE, 2017 (송영수, Wachirawit Ponghiran, 심성보)
"Timing-aware wire width optimization for SADP process" (송영수)
"Cut mask optimization for multi-patterning directed self-assembly lithography" (Wachirawit Ponghiran, 심성보)
Journal paper accepted to IEEE TCAD, 2016 (심성보)
"Fast verification of guide patterns for directed self-assembly lithography"
Internship at IMEC, Belgium, 2016.6 - 2016.9 (최수형)    Photo photos
Worked on optical-proximity-correction (OPC)
Conference paper accepted to ICCAD, 2016 (정진욱)
"OWARU: free space-aware timing-driven incremental placement"
Conference paper accepted to ISOCC, 2016 (윤기원, 최수형)
"Area efficient neuromorphic circuit based on stochastic computation"
Conference paper accepted to ICCE, 2016 (김상민)
"Synthesis of dual-mode circuits through optimizing transition time constraints"
DAC Richard Newton young fellow award, 2016 (최수형) Photo photos
The award is named to honor the memory of Dr. A. Richard Newton, a towering figure in EDA, DAC and education.
Conference paper accepted to DAC + SIGDA Ph.D forum, 2016 (심성보) Photo photos
"Redundant via insertion for multiple-patterning directed-self-assembly lithography"
Internship at IBM T. J. Watson Research Center, US, 2016.1 - 2016.7 (정우현) Photo photos
Worked on physical retiming and latch placement & cloning
Journal paper accepted to IEEE TVLSI, 2016 (심성보, 정우현)
"Lithography defect probability and its application to physical design optimization"
Journal paper accepted to ACM TODAES, 2016 (김상민)
"Synthesis of dual-mode circuits through library design, gate sizing, and clock tree optimization"
Conference paper invited to ICICDT, 2016 (심성보) Photo photos
"Placement optimization for MP-DSAL compliant layout"
Conference paper accepted to ICICDT, 2016 (한인학)
"Register grouping for synthesis of clock gating logic"
Conference paper invited to APCCAS, 2016 (심성보, 최수형)
"Machine learning (ML)-based lithograph optimizations"
Conference paper accepted to ISCAS, 2016 (윤기원) Photo photos
"Crosslink insertion for minimizing OCV clock skew"
Tutorial at ASP-DAC, 2016 (심성보) Photo photos
"Directed self-assembly lithography (DSAL): mask synthesis and circuit design"
Internship at IBM T. J. Watson Research Center, US, 2015.7 - 2015.12 (정진욱) Photo photos
Worked on timing driven incremental placement