Gate-Level Clock Gating

In sequential cells such as Flip-flop, Clock networks consume more than 40% of the circuit’s total power consumption on average. Therefore, it is important to reduce the power consumption of the clock network for low-power design, and for this purpose, clock gating is used to supply clocks only when the signal of the flip-flop is switched.

We note that a simpler gating function can be derived from a cyclic path that connects the input and output of the same register. A key problem in this approach is to extract a set of cyclic paths of each register, such that power consumption is minimized. We suggest Alogorithm for that problem and simplify the cyclic paths by using don’t care condition and AND/OR gate.

Power Gating Switch Sizing

Power gating is a technique in which a current switch is inserted to reduce leakage current. A circuit is cut off from its power supply in sleep mode by means of a current switch.

When designing a power-gated circuit, it is important to appropriately determine the size of the current switch. The switch must be bigger such that there is no measurable voltage (IR) drop across it. However, in terms of leakage current and area consumption, the smaller the switch, the better. In this work, we aim to derive the optimal size by considering power network and power gating together by using machine learning.

NTV Circuit Design

Near threshold voltage (NTV) circuits are designed to achieve maximum energy efficiency by lowing the operating voltage. Near threshold voltage (NTV) circuits’ supply voltage is a little larger than threshold voltage. Thus, NTV circuit design has been considered for such applications as IoT where ultra-low power is important.

In NTV, a circuit suffers from a large increase in delay and in delay variation. They can seriously affect clock frequency, energy dissipation and circuit area. Figure shows one example of introduced methodology which is optimizing the transistor lengths due to RSCE, to decrease cell delay and delay variation.

Dual Edge-Triggered Flip-Flop

Unlike single edge-triggered flip-flop(SETFF) which is only triggered at the charging or falling edge of a clock signal, dual edge-triggered flip-flop(DETFF) is triggered at both charging and falling edge. DETFF allows us to use whole clock signal while keeping the same throughput. This implies that we can greatly decrease clock power consumption since clock network takes large proportion of total power. However, the DETEF is not being used due to irregular clock H/L ratio and difficulty in timing analysis. In order to solve problems, we propose timing analysis method.

Timing analysis method measures multiple required arrival times(RATs) and then finds the single RAT like dotted region because single RAT can be processed by conventional timing analysis.