Umar Afzaal

Post-Doc. researcher, School of EE, KAIST

  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • Chosun University, College of IT Convergence, Department of Computer Engineering Ph.D (Sep. 2018 – Aug. 2021)
  • Chosun University, College of IT Convergence, Department of Computer Engineering M.S.(Sep. 2016 – Aug. 2018)
  • NED University of Science & Technology, School of Electrical & Computer Engineering B.E (Jan. 2012 – Dec. 2015)
  • Malir Cantonment Government Degree Science & Commerce College, Karachi, Pakistan (Aug. 2009 – Sep. 2011)

Honors

Research Interests

  • Evolutionary high-level circuit synthesis (HLS)
  • Fault-tolerance circuit design

Experiences

  • Manufacturing support @ Canoga Perkins
  • Senior firmware engineer @ SysTellex Inc.
  • Postdoctoral researcher @ Computer systems lab, Chosun Univ. (Aug. 2021 – Dec. 2021)
  • Graduate research associate @ Computer systems alb, Chosun Univ. (2016 – 2021)

Publications

Journal Papers

  1. Umar Afzaal, Abdus Sami Hassan, and Jeong-A. Lee, “Improved error detection performance of logic implication checking in FPGA circuits,” Microprocessors and Microsystems, vol. 78, pp. 103179/1-8, Oct. 2021.
  2. Inayat Ullah, Zahid Ullah, Umar Afzaal, and Jeong-A. Lee, “DURE: An energy- and resource-efficient TCAM architecture for FPGAs with dynamic updates,” IEEE Transactions on Very Large Scale Integration Systems, vol. 27, no. 6, pp. 1298-1307, Mar. 2019.
  3. Umar Afzaal and Jeong-A. Lee, “A self-checking TMR voter for increased reliability consensus voting in FPGAs.” IEEE Transactions on Nuclear Science, vol. 65, no. 5 pp. 1133-1139, Apr. 2018.
  4. Abdus Sami Hassan, Umar Afzaal, Tooba Arifeen, and Jeong A. Lee, “Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection.” Electronics, vol. 7, no. 10 pp. 258/1-15, Oct. 2018.

Conference Papers

  1. Umar Afzaal, and Jeong-A. Lee. “Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation,” Proc. Euromicro Conf. on Digital System Design (DSD), Aug. 2020.
  2. Umar Afzaal, Abdus Sami Hassan, Tooba Arifeen, and Jeong A. Lee, “Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking,” Proc. Euromicro Conf. on Digital System Design (DSD), Aug. 2018.
  3. Umar Afzaal and Jeong A. Lee, “FPGA-based design of a self-checking TMR voter,” Proc. Int’l Conf. on Field Programmable Logic and Applications (FPL), Sep. 2017.
  4. Umar Afzaal, and Jeong-A. Lee, “Low-cost Hardware Redundancy for Fault-mitigation in Power-constrained IoT Systems,” Proc. Int’l Conf. on Information and Communication Technology Convergence (ICTC), Oct. 2020.
  5. Inayat Ullah, Umar Afzaal, Zahid Ullah, and Jeong-A. Lee, “High-speed configuration strategy for configurable logic block-based TCAM architecture on FPGA,” Proc. Euromicro Conf. on Digital System Design (DSD), Aug. 2018.