FAMILY

Design Technology Lab

Suhyeong Choi (최수형)

Samsung Electronics

  • Last update
    August 12, 2021

Education

  • KAIST, School of Electrical Engineering M.S. (Mar. 2016 – Feb. 2018)
  • KAIST, School of Electrical Engineering B.S. (Mar. 2011 – Feb. 2016)
  • Gyeongbuk Science High School (Mar. 2009 – Feb. 2011)

Research Interests

  • Thermal analysis
  • Optical proximity correction (OPC)
  • Neuromorphic hardware

Experiences

  • Engineer, Semiconductor Research Center, Samsung Electronics (Jan. 2021 – Present)
  • Researcher, Koh Young Technology (Jan. 2018 – Dec. 2020)
  • Intern, IMEC, Belgium (Jan. 2017 – Feb. 2017)
  • Intern, IMEC, Belgium (Jun. 2016 – Sep. 2016)
  • Richard Newton Young Student Fellow Award @ the 53rd DAC (Jun. 2016)

Publications

Journal Papers

  1. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Neural network classifier-based OPC with imbalanced training data,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 38, no. 5, pp. 938-948, May. 2019.
  2. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Electrothermal analysis with non-convective boundary conditions,” IEEE Transactions on Circuits and Systems II, vol. 65, no. 8, pp. 1044-1048, Aug. 2018.
  3. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, “Light interference map: a prescriptive optimization of lithography-friendly layout,” IEEE Transactions on Semiconductor Manufacturing, vol. 29, pp.44-49, Feb. 2016.

Conference Papers

  1. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, “Machine learning-based 3D resist model,” Proc. SPIE Advanced Lithography, Feb. 2017.
  2. Suhyeong Choi, Jae Uk Lee, Victor Blanco, Ryoung-Han Kim, and Youngsoo Shin, “2D self-aligned via patterning strategy with EUV single exposure in 3nm technology,” Proc. SPIE Advanced Lithography, Feb. 2017.
  3. Suhyeong Choi, Jae Uk Lee, Victor Blanco, Peter Debacker, Praveen Raghavan, Ryoung-Han Kim, and Youngsoo Shin, “Large marginal 2D self-aligned via patterning for sub-5nm technology,” Proc. SPIE Advanced Lithography, Feb. 2017.
  4. Kiwon Yoon, Suhyeong Choi, and Youngsoo Shin, “Area efficient neuromorphic circuit based on stochastic computation,” Proc. Int’l SoC Design Conf. (ISOCC), Oct. 2016.
  5. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, “Machine learning (ML)-based lithography optimization,” Proc. Asia Pacific Conf. on Circuits and Systems (APCCAS), Oct. 2016.
  6. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Machine learning (ML)-guided OPC using basis functions of polar Fourier transform,” Proc. SPIE Advanced Lithography, Feb. 2016.
  7. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Electrothermal analysis with generalized boundary conditions,” Proc. Int’l SoC Design Conf. (ISOCC), Nov. 2015.