Design Technology Lab

Seunggyu Lee (이승규)

Ph.D. candidate, School of EE, KAIST

  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219


  • KAIST, School of Electrical Engineering Ph.D. (M.S. integrated) (Mar. 2022 – Present)
  • KAIST, School of Electrical Engineering M.S. (Mar. 2021 – Feb. 2022)
  • Hanyang University, School of Electronic Engineering B.S. (Mar. 2015- Feb. 2021)
  • Dongin High school (Mar. 2011 – Feb. 2014)


Research Interests

  • Design methodology for processing-in-memory (PIM)
  • Machine learning for 3D memory


Journal Papers

Conference Papers

  1. Seunggyu Lee, Gangmin Cho, Wonjae Lee, Umar Afzaal, and Youngsoo Shin, “Efficient netlist rewriting and in-memory mapping for memristor-aided logic,” Proc. Design Automation Conf. (DAC), submitted.