Design Technology Lab

DT LAB   →  M.S. Candidates   →  Seohyun Kim (김서현)

Seohyun Kim (김서현)

M.S. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering M.S. (Mar. 2024 – Present)
  • KAIST, School of Electrical Engineering B.S. (Mar. 2019 – Feb. 2024)
  • Pohang Jecheol High School (Mar. 2016 – Feb. 2019)

Research Interests

Honors

  1. ISE President Best Paper Award @ 2024 Int’l SoC Design Conf. (ISOCC)

Honors

Experiences

  • Internship @ Samsung Electronics (Jan. 2021 – Feb. 2021)

Publications

Journal Papers

  1. Seohyun Kim, Shilong Zhang, and Youngsoo Shin, “ML-guided curvilinear OPC: fast, accurate, and manufacturable curve correction,” IEEE Transactions on Semiconductor Manufacturing, vol. 38, no. 1, pp. 19-28, Feb. 2025.

Conference Papers

  1. Shilong Zhang, Seohyun Kim, and Youngsoo Shin, “Fast and accurate matrix-OPC with MEEF prediction using Kolmogorov-Arnold network,” Proc. SPIE Advanced Lithography, submitted.
  2. Seohyun Kim, Gangmin Cho, Shilong Zhang, and Youngsoo Shin, “Fast and accurate curvilinear OPC with ML-guided curve correction,” Proc. Int’l SoC Design Conf. (ISOCC), Aug. 2024. (ISE President Best Paper Award)
  3. Gangmin Cho, Taeyoung Kim, Seohyun Kim, and Youngsoo Shin, “A fast and accurate PEB simulation through recurrent neural network,” Proc. SPIE Advanced Lithography, Feb. 2024.
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