Design Technology Lab

DT LAB   →  M.S. Candidates   →  Minseung Shin (신민승)

Minseung Shin (신민승)

M.S. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering M.S. (Sep. 2023 – Present)
  • Kyungpook National University, School of Electrical Engineering B.S. (Mar. 2018 – Aug. 2023)
  • Gimhae Daecheong High School (Mar. 2015 – Feb. 2018)

Research Interests

  • Fast on-chip PDN analysis & optimization

Experiences

  • Internship @ Samsung Electronics (Jul. 2022 – Aug. 2022)

Honors

Publications

Journal Papers

Conference Papers

  • Minseung Shin, Jongbeom Kim, Yunjeong Shin, and Taigon Song, “A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond,” Proc. Int’l SoC Design Conf. (ISOCC), accepted.
  • Hyunsoo Lee, Hyundong Lee, Minseung Shin, Gyuri Shin, Sumin Jeon, and Taigon Song, “High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture,” Proc. Int’l SoC Design Conf. (ISOCC), accepted.
COPYRIGHT (c) 2021. DT LAB. All rights reserved. 5219, School of Electrical Engineering (E3-2), KAIST 291 Daehak-ro, Yuseong-gu, Daejeon 34141, KOREA / Tel: +82-42-350-5479 / Fax: +82-42-350-5479 / Previous homepage: https://sites.google.com/view/kaist-shinlab