Minseung Shin (신민승)
M.S. candidate, School of EE, KAIST
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- Email
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location291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
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OfficeSchool of Electrical Engineering (E3-2), 5219
Education
- KAIST, School of Electrical Engineering M.S. (Sep. 2023 – Present)
- Kyungpook National University, School of Electrical Engineering B.S. (Mar. 2018 – Aug. 2023)
- Gimhae Daecheong High School (Mar. 2015 – Feb. 2018)
Research Interests
- Machine learning for EDA
- RTL-level power estimation
- On-chip PDN analysis and optimization for DRAM design
Experiences
- Internship @ Samsung Electronics (Jul. 2022 – Aug. 2022)
Honors
Publications
Journal Papers
Conference Papers
- Minseung Shin, Shilong Zhang, and Youngsoo Shin, “Fast and Accurate Analysis of Power Distribution Network Impedance for DRAM Design,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), submitted.
- Minseung Shin, Jongbeom Kim, Yunjeong Shin, and Taigon Song, “A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond,” Proc. Int’l SoC Design Conf. (ISOCC), Oct. 2023.
- Hyunsoo Lee, Hyundong Lee, Minseung Shin, Gyuri Shin, Sumin Jeon, and Taigon Song, “High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture,” Proc. Int’l SoC Design Conf. (ISOCC), Oct. 2023.