Design Technology Lab

DT LAB   →  Ph.D. Candidates   →  Min Kim (김민)

Min Kim (김민)

Ph.D. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering Ph.D. (M.S. integrated) (Sep. 2024 – Present)
  • Sungkyunkwan University, School of Electronic Engineering B.S. (Mar. 2007- Feb. 2013)
  • Geumseong High School (Mar. 2003 – Feb. 2006)

Research Interests

  • Machine learning for EDA

Experiences

  • Foundry Division, Samsung Electronics (Jan. 2013 – Aug. 2024)
  • Internship @ Samsung Electronics (Dec. 2011 – Feb. 2012)

Publications

Journal Papers

  1. Min Kim, Seohyun Kim, and Youngsoo Shin, “On-chip warpage extraction through ring oscillator delay testing,” IEEE Transactions on Very Large Scale Integration Systems, accepted. 

Conference Papers

  1. Min Kim, Seohyun Kim, and Youngsoo Shin, “Warpage-induced delay variability: modeling timing derating factors,” Proc. IEEE/JSAP Symp. on VLSI Technology & Circuits, submitted.
  2. Min Kim, Shilong Zhang, Geuna Chang, and Youngsoo Shin, “Signal-integrity-aware routing and shielding for UCIe-compliant 2.5D ICs,” Proc. Workshop on Signal and Power Integrity (SPI), accepted.
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