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DT LAB   →  Alumni   →  Jinwook Jung (정진욱)

Jinwook Jung (정진욱)

Research Staff Member, IBM Thomas J. Watson Research Center
  • Last update
    Aug 17, 2021

Education

  • KAIST, School of Electrical Engineering Ph.D. (Sept. 2013 – Feb. 2018)
  • Kobe University, Graduate School of System Informatics M.E. (Apr. 2011 – Mar. 2013)
  • Kobe University, Department of Computer Science and Systems Engineering B.E. (Apr. 2007 – Mar. 2011)

Experiences

  • Research Staff Member, IBM Thomas J. Watson Research Center, Yorktown Heights, NY (Nov. 2018 – Present)
  • Postdoctoral Researcher, KAIST, Daejeon, Korea (Mar. 2018 – Nov. 2018)

Publications

Journal Papers

  1. Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, and Youngsoo Shin, “Cut optimization for redundant via insertion in self-aligned double patterning,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 6, pp. 61:1-61:21, Sep. 2019.
  2. Jinwook Jung, Gi-Joon Nam, Woohyun Chung, and Youngsoo Shin, “Integrated latch placement and cloning for timing optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 2, pp. 22:1-22:17, Feb. 2019.
  3. Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, “OWARU: Free Space-Aware Timing-Driven Incremental Placement with Critical Path Smoothing,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 37, no. 9, pp. 1825-1838, Sep. 2018.
  4. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, and Masahiko Yoshimoto,  “A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation,” IEICE Trans. Electronics, vol. E97-C, no. 4, pp. 332-341, Apr. 2014.
  5. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM,” IEICE Trans. Electronics, vol. E96-C, no. 4, pp.528-537, Apr. 2013.

Conference Papers

  1. Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi Reddy, Alexey Lvov, Gi-Joon Nam, and Jiang Hu, “FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2021.
  2. Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonano, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-hyoun Kim, Siyu Koswatta, Saekyu Lee, Martin Lutz, Silvia Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matt Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian Curran, Sunil Shukla, Leland Chang, and Kailash Gopalakrishnan, “RaPiD: AI Accelerator for Ultra-Low Precision Training and Inference,” International Symposium on Computer Architecture (ISCA), June 2021.
  3. Ismail Bustany, Jinwook Jung, Patrick Madden, Natarajan Viswanathan, and Stephen Yang, “Still Benchmarking after All These Years,” in Proceedings of International Symposium on Physical Design (ISPD), Mar. 2021.
  4. Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce Fleischer, Michael Guillorn, Matt Cohen, Silvia Melitta Müller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kh Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian Curran, Viji Srinivasan, Pong-fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan, “A 7nm 4-Core AI Chip with 25.6 TFLOPS Hybrid FP8 Training, 102.4 TOPS INT4 Inference, and Workload-Aware Throttling,” International Solid-State Circuits Conference (ISSCC), Feb. 2021.
  5. Arjun Chaudhuri, Jonti Talukdar, Jinwook Jung, Gi-Joon Nam, and Krishnendu Chakrabarty, “Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks,” in Proceedings of Design Automation and Test in Europe (DATE), Feb. 2021.
  6. Siyuan Chen, Jinwook Jung, Peilin Song, Krishnendu Chakrabarty, and Gi-Joon Nam, “BISTLock: Efficient IP Piracy Protection using BIST,” Proceedings of the International test Conference (ITC), Nov. 2020.
  7. Jianli Chen, Iris Hui Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih Lang Li, Shih Ting Lin, Mingyu Woo, “DATC RDF-2020: Strengthening the Foundation for AcademicResearch in IC Physical Design,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2020.
  8. Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, and Gi-Joon Nam, “Routing-Free Crosstalk Prediction,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2020.
  9. Jianli Chen, Iris Hui Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih Lang Li, Shih Ting Lin, Mingyu Woo, “DATC RDF-2019: Towards a complete academic reference design flow,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2019.
  10. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Standard cell layout design and placement optimization for TFET-based circuits,” in Proceedings of International Symposium on Circuits and Systems (ISCAS), May 2019
  11. Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, and Gi-Joon Nam, “DATC RDF: An Open Design Flow From Logic Synthesis to Detailed Routing,” in Proceedings of the ICCAD’18 Workshop on Open-Source EDA Technology, Nov. 2018.
  12. Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, and Gi-Joon Nam, “DATC RDF: From Logic Synthesis to Detailed Routing,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2018.
  13. Jingon Lee, Jinwook Jung, and Youngsoo Shin, “Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits,” in Proceedings of International Symposium on Circuits and Systems (ISCAS), May 2018.
  14. Yonghwi Kwon, Jinwook Jung, Inhak Han, and Youngsoo Shin, “Transient Clock Power Estimation of Pre-CTS Netlist,” in Proceedings of International Symposium on Circuits and Systems (ISCAS), May 2018.
  15. Jaewoo Seo, Jinwook Jung, and Youngsoo Shin, “A Compact Multi-Bit Flip-Flop with Smaller Height Implementation and Metal-Less Clock Routing,” in Proceedings of SPIE Advanced Lithography, Feb. 2018.
  16. Youngsoo Song, Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Timing Optimization in SADP Process through Wire Widening and Double Via Insertion,” in Proceedings of SPIE Advanced Lithography, Feb. 2018.
  17. Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Darav, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, and Yih-Lang Li, “DATC RDF: Robust Design Flow Database,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2017.
  18. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant Via Insertion in SADP Process with Cut Merging and Optimization,” in Proceedings of the 25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2017.
  19. Jaewoo Seo, Jinwook Jung, and Youngsoo Shin, “Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization,” in Proceedings of Design Automation Conference (DAC), June 2017.
  20. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning,” in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), May 2017.
  21. Youngsoo  Song, Jinwook Jung, and Youngsoo Shin, “Redundant Via Insertion in Self-Aligned Double Patterning,” Proceedings of SPIE Advanced Lithography, Feb. 2017.
  22. Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, and Yih-Lang Li “OpenDesign Flow Database: The Infrastructure for VLSI Design and Design Automation Research,” in Proceedings of the  IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2016.
  23. Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, “OWARU: Free Space-Aware Timing-Driven Incremental Placement,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2016.
  24. Jinwook Jung and Youngsoo Shin, “Localized DNA Circuit Design with Majority Gates,” in Proceedings of the 12th BioMedical Circuits and Systems Conference (BioCAS), Oct. 2016.
  25. Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Physical Synthesis of DNA Circuits with Spatially Localized Gates,” Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD), Oct. 2015.
  26. Jinwook Jung, Dongsu Lee, and Youngsoo Shin, “Design and Optimization of Multiple-Mesh Clock Network,” in Proceedings of the 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2014, pp. 171-176.
  27. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement,” in Proceedings of the 15th International Symposium on Quality Electronic Design (ISQED), Mar. 2014, pp.16-23.
  28. Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, and Hiroshi Kawaguchi, “Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting All-Zero-Data Flags,” in Proceedings of the 14th International Symposium on Quality Electronic Design (ISQED), Mar. 2013, pp.216-222.
  29. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi and Masahiko Yoshimoto, “A Variation-Aware 0.57-V Set-Associative Cache with Mixed Associativity Using 7T/14T SRAM,” in Proceedings of the 11th IEEE Faible Tension Faible Consommation (IEEE FTFC), June 2012, pp.1-4.
  30. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi and Masahiko Yoshimoto, “256-KB Associativity-Reconfigurable Cache with 7T/14T SRAM for Aggressive DVS Down to 0.57 V,” in Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems (IEEE ICECS), Dec. 2011, pp.524-527.

Patents

  1. Jaewoo Seo, Jinwook Jung, Youngsoo Shin, “Semiconductor Device,” Korean patent P-2018-0005928, Jan. 2018.
  2. Jaewoo Seo, Jinwook Jung, Youngsoo Shin, “Semiconductor Device,” Korean patent P-2018-0000818, Jan. 2018.
  3. Jinwook Jung, Frank Musante, Gi-Joon Nam, Shyam Ramji, Lakshmi Reddy, Gustavo Tellez, and Cindy S. Washburn, “Critical Path Straightening System Based On Free-Space Aware and Timing Driven Incremental Placement,” US patent 2018-0121575A1. Nov. 2016.
  4. Hiroshi Kawaguchi, Masahiko Yoshimoto, Yohei Nakata, and Jinwook Jung, “Nonvolatile Memory Cache,” Japanese patent 2014-153965, Feb. 11, 2013.
  5. Masahiko Yoshimoto, Hiroshi Kawaguchi, Yohei Nakata, Shunsuke Okumura, and Jinwook Jung, “Low-Voltage Cache with Mixed-Associativity,” Japanese patent 2016-6024897.

Book

  1. Takashi Sato, Masanori Hashimoto, Shuhei Tanakamaru, Ken Takeuchi, Yasuo Sato, Seiji Kajihara, Masahiko Yoshimoto, Jinwook Jung, Yuta Kimi, Hiroshi Kawaguchi, Hajime Shimada, and Jun Yao, “Time-Dependent Degradation in Device Characteristics and Countermeasures by Design,” Chapter 6, VLSI Design and Test for Systems Dependability, Springer, 2019.
  2. Jinwook Jung, Dongsoo Lee, and Youngsoo Shin, “Design and Optimization of Multiple-Mesh Clock Network,” Chapter 3, VLSI-SoC: Internet of Things Foundations, Springer, 2015.
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