Design Technology Lab

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Insu Cho (조인수)

M.S. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering M.S. (Mar. 2022 – Present)
  • Hanyang University, School of Electronic Engineering B.S. (Mar. 2016- Feb. 2022)
  • Suji High School (Mar. 2013 – Feb. 2016)

Honors

Design methodology for advanced technology,  GPU acceleration for CAD algorithm

Research Interests

  • Machine learning for EDA
  • Power gating

Experiences

  • Internship @ Samsung Electronics (Sep. 2021 – Dec. 2021)

Publications

Journal Papers

Conference Papers

  1. Wonjae Lee, Insu Cho, Gangmin Cho, and Youngsoo Shin, “Routability-driven power distribution network synthesis with IR-drop budgeting,” Proc. Workshop on Machine Learning for CAD (MLCAD), Sep. 2023.
  2. Daijoon Hyun, Younggwang Jung, Insu Cho, and Youngsoo Shin, “Decoupling capacitor insertion minimizing IR-drop violations and routing DRVs,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2023.
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