KAIST, School of Electrical Engineering Ph.D. (Feb. 2012 – Jun. 2017)
KAIST, School of Electrical Engineering M.S. (Feb. 2010 – Feb. 2012)
KAIST, School of Electrical Engineering B.S. (Mar. 2005 – Feb. 2010)
Seoul Science High School (Mar. 2003 – Feb. 2005)
Research Interests
Timing analysis
Thermal analysis
Logic synthesis
Pulsed latch circuits
Clock gating
Dual edge-triggered flip-flop
Experiences
Internship @ Samsung Electronics (Jul. 2015 – Aug. 2015)
Internship @ LGE (Oct. 2013 – Apr. 2014)
Richard Newton Young Fellow Award at the 50th DAC (Jun. 2013)
Internship @ IBM ARL (Jul. 2011 – Oct. 2011)
Publications
Journal Papers
Inhak Han and Youngsoo Shin, “Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops,” ACM Transactions on Design Automation of Electronic Systems (ToDAES), vol. 23, no. 5, pp. 61:1-61:21, Aug. 2018.
Inhak Han and Youngsoo Shin, “Simplifying clock gating logic by matching factored forms,” IEEE Transactions on Very Large Scale Integration Systems(TVLSI), vol. 22, no. 6, pp. 1338-1349, Jun. 2014.
Seungwhun Paik, Inhak Han, Sangmin Kim, and Youngsoo Shin, “Clock gating synthesis of pulsed-latch circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems(TCAD), vol. 31, no. 7, pp. 1019-1030, Jul. 2012.
Conference Papers
Yonghwi Kwon, Inhak Han, and Youngsoo Shin “Clock gating synthesis of netlist with cyclic logic paths,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2019.
Yonghwi Kwon, Jinwook Jung, Inhak Han, and Youngsoo Shin “Transient clock power estimation of pre-CTS netlist,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May. 2018.
Inhak Han, Jonggyu Kim, Joonhwan Yi, and Youngsoo Shin “Register grouping for synthesis of clock gating logic,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), Jun. 2016.
Inhak Han, Daijoon Hyun, and Youngsoo Shin, “Buffer insertion to remove hold violations at multiple process corners,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2016.
Inhak Han and Youngsoo Shin “Folded circuit synthesis: logic simplification using dual edge-triggered flip-flops,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), May. 2013.
Inhak Han and Youngsoo Shin “Synthesis of clock gating logic through factored form matching,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), May. 2012.
Jaeha Kung, Inhak Han, and Youngsoo Shin “Thermal signature: a simple yet accurate thermal index for floorplan optimization,” Proc. Design Automation Conf. (DAC), Jun. 2011.
Sangmin Kim, Inhak Han, Seungwhun Paik, and Youngsoo Shin, “Pulser gating: a clock gating of pulsed-latch circuits,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2011.
Inhak Han, Lee-eun Yu, and Youngsoo Shin “Fast monte carlo method via reduced sample number and node filtering,”Proc. Int’l Conf. on IC Design & Technology (ICICDT), Jun. 2010.
