FAMILY

Design Technology Lab

Daijoon Hyun (현대준)

Assistant Professor, Cheongju University

  • Last update
    August 9, 2021

Education

  • KAIST, School of Electrical Engineering Ph.D. (Mar. 2015 – Aug. 2019)
  • Pohang University of Science and Technology, School of Electrical Engineering M.E. (Mar. 2006 – Feb. 2008)
  • Hanyang University, School of Electrical Engineering B.E. (Mar. 1999 – Feb. 2006)
  • Seoul High School (Mar. 1995 – Feb. 1998)

Research Interests

  • Design methodology for advanced technology: airgap, SADP, SIV, etc.
  • Machine-learning for computer-aided design
  • Model-to-hardware correlation (MHC) based design methodology
  • Near threshold voltage (NTV) design
  • Interconnect corner modeling

Experiences

  • Assistant Professor, School of Electrical Engineering, Cheongju University (Sep. 2020 – Present)
  • Foundry Business, Samsung Electronics (Sep. 2019 – Sep. 2020)
  • Student research forum (SRF) @ ASPDAC (Jan. 2017)
  • System LSI Business, Samsung Electronics (Aug. 2008 – Feb. 2015)
  • Internship @ FineSim team of Magma-DA (Dec. 2007 – Jun. 2008)
  • Research Assistant @ POSTECH (Mar. 2007 – Aug. 2007)

Honors

  • 우수발표논문상 @ SoC 학술대회: 2nd author (May 2018)
  • Student research forum (SRF) @ ASPDAC (Jan. 2017)
  • Best paper award @ ISOCC (Nov. 2015)

Publications

Journal Papers

  1. Daijoon Hyun, Sunwha Koh, Younggwang Jung, Taeyoung Kim, and Youngsoo Shin, “Routability optimization of extreme aspect ratio design through non-uniform placement utilization and selective flip-flop stacking,” ACM Transactions on Design Automation of Electronic Systems, in revision.
  2. Daijoon Hyun, Younggwang Jung, and Youngsoo Shin, “Airgap insertion and layer reassignment under setup and hold timing constraints,” IEEE Transactions on CAD of Integrated Circuits and Systems, accepted.
  3. Daijoon Hyun, Younggwang Jung, and Youngsoo Shin, “Selective use of stitch-induced via for V0 mask reduction: standard cell design and placement optimization,” IEICE Transactions on Fundamentals of Electonics, Communications and Computer Sciences, vol. E102.A, no. 12, pp. 1711-1719, Dec. 2019.
  4. Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, and Youngsoo Shin, “Cut optimization for redundant via insertion in self-aligned double patterning,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 6, pp. 61:1-61:21, Sep. 2019.
  5. Daijoon Hyun and Youngsoo Shin, “Integrated approach of airgap insertion for circuit timing optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 2, pp. 24:1-24:22, Feb. 2019.

Conference Papers

  1. Sunwha Koh, Younggwang Jung, Daijoon Hyun, and Youngsoo Shin, “Routability optimization for extreme aspect ratio design using convolutional neural network,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May. 2021.
  2. Yonghwi Kwon, Daijoon Hyun, Giyoon Jung, and Youngsoo Shin, “Dynamic IR drop prediction using image-to-image translation neural network,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May. 2021.
  3. Younggwang Jung, Daijoon Hyun, and Youngsoo Shin, “Integrated airgap insertion  and layer reassignment for circuit timing optimization,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 32-37, Jan. 2020. (Nominated for Best Paper Award)
  4. Daijoon Hyun, Yuepeng Fan, and Youngsoo Shin, “Accurate wirelength prediction for placement-aware synthesis through machine learning,” Proc. Design, Automation & Test in Europe (DATE), pp. 324-327, Mar. 2019.
  5. Kiwon Yoon, Daijoon Hyun, and Youngsoo Shin, “Fast timing analysis of non-tree clock network with shorted wires,” Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 279-284, May. 2018.
  6. Daijoon Hyun, Jaewoo Seo, and Youngsoo Shin, “Library optimization for near threshold voltage design,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), pp. 1-4, May. 2018.
  7. Youngsoo Song, Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Timing optimization in SADP process through wire widening and double via insertion,” Proc. SPIE Advanced Lithography, pp. 105880R-1-105880R-8, Feb. 2018.
  8. Daijoon Hyun and Youngsoo Shin, “Automatic insertion of airgap with design rule constraints,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 381-386, Jan. 2018.
  9. Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin, “Clock tree optimization through selective airgap insertion,” Proc. Int’l Symp. on Quality Electronic Design (ISQED), pp. 203-208, Mar. 2017.
  10. Daijoon Hyun and Youngsoo Shin, “Selection of airgap layers for circuit timing optimization,” Proc. SPIE Advanced Lithography, pp. 101480O-1-101480O-8, Feb. 2017.
  11. Daijoon Hyun and Youngsoo Shin, “Modeling interconnect corners under double patterning misalignment,” Proc. SPIE Advanced Lithography, pp. 97810F-1-97810F-7, Feb. 2016.
  12. Daijoon Hyun and Youngsoo Shin, “Calibration of interconnect corners using on-chip ring oscillators,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 39-40, Nov. 2015. (Best Paper Award)
  13. Inhak Han, Daijoon Hyun, and Youngsoo Shin, “Buffer insertion to remove hold violations at multiple process corners,”  Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 232-237, Jan. 2016.
  14. Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Physical synthesis of DNA circuits with spatially localized gates,” Proc. Int’l Conf. on Computer Design (ICCD), pp. 280-286, Oct. 2015.