JOURNAL & CONFERENCE

2022

Yonghwi Kwon and Youngsoo Shin, “SRAF print fix using class activation map and PVB width gradient,” Proc. Design, Automation & Test in Europe (DATE), submitted.
Younggwang Jung, Youngsoo Shin, and Daijoon Hyun, “Timing-aware airgap insertion and layer reassignment under setup and hold constraints,” IEEE Transactions on CAD of Integrated Circuits and Systems, submitted.
Yonghwi Kwon and Youngsoo Shin, “Context-aware fast optical proximity correction using bidirectional recurrent neural network,” Proc. SPIE Advanced Lithography, submitted.
Gangmin Cho, Byungho Choi, Yonghwi Kwon, and Youngsoo Shin, “Refragmentation through machine learning classifier for fast optical proximity correction,” Proc. SPIE Advanced Lithography, submitted.
Byungho Choi, Gangmin Cho, Yonghwi Kwon, and Youngsoo Shin, “Synthesis of hotspot patterns using generative network trained with hotspot probability,” Proc. SPIE Advanced Lithography, submitted.

2021

Yonghwi Kwon and Youngsoo Shin, “Optical proximity correction using bidirectional recurrent neural network with attention mechanism,” IEEE Transactions on Semiconductor Manufacturing, vol. 34, no. 2, pp. 168-176, May 2021.paper
Sunwha Koh, Younggwang Jung, Daijoon Hyun, and Youngsoo Shin, “Routability optimization for extreme aspect ratio design using convolutional neural network,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May 2021.paper
Yonghwi Kwon, Daijoon Hyun, Giyoon Jung, and Youngsoo Shin, “Dynamic IR drop prediction using image-to-image translation neural network,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May 2021.paper
Youngsoo Shin, “Computational lithography using machine learning models,” IPSJ Transactions on System LSI Design Methodology, vol. 14, pp. 2-10, Feb. 2021. (Invited Paper)paper
Gangmin Cho, Yonghwi Kwon, Pervaiz Kareem, Sungho Kim, and Youngsoo Shin, “Test pattern extraction for lithography modeling under design rule revisions,” Proc. SPIE Advanced Lithography, Feb. 2021.paper
Pervaiz Kareem, Yonghwi Kwon, Gangmin Cho, and Youngsoo Shin, “Fast prediction of process variation band through machine learning models,” Proc. SPIE Advanced Lithography, Feb. 2021.paper
Yonghwi Kwon and Youngsoo Shin, “Optimization of accurate resist kernels through convolutional neural network,” Proc. SPIE Advanced Lithography, Feb. 2021.paper
Pervaiz Kareem and Youngsoo Shin, “Synthesis of lithography test patterns using machine learning model,” IEEE Transactions on Semiconductor Manufacturing, vol. 34, no. 1, pp. 49-57, Feb. 2021. paper

2020

Wonjae Lee, Yonghwi Kwon, and Youngsoo Shin, “Fast ECO leakage optimization using graph convolutional network,” Proc. Great Lakes Symp. on VLSI (GLSVLSI), Sep. 2020. (Best Paper Award Candidate)paper
Sunwha Koh, Yonghwi Kwon, and Youngsoo Shin, “Pre-layout clock tree estimation and optimization using artificial neural network,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), Aug. 2020.paper
Pervaiz Kareem, Yonghwi Kwon, and Youngsoo Shin, “Layout pattern synthesis for lithography optimizations,” IEEE Transactions on Semiconductor Manufacturing, vol. 33, no. 2, pp. 283-290, May 2020. paper
Yonghwi Kwon, Jinho Yang, Sungho Kim, Cheolkyun Kim, and Youngsoo Shin, “SRAF printing prediction using artificial neural network,” Proc. SPIE Advanced Lithography, Feb. 2020.paper
Younggwang Jung, Daijoon Hyun, and Youngsoo Shin, “Integrated airgap insertion and layer reassignment for circuit timing optimization,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 32-37, Jan. 2020. (Best Paper Award Candidate)paper

2019

Daijoon Hyun, Younggwang Jung, and Youngsoo Shin, “Selective use of stitch-induced via for V0 mask reduction: standard cell design and placement optimization,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102.A, no. 12, pp. 1711-1719, Dec. 2019. paper
Cheongwon Lee, Youngsoo Song, and Youngsoo Shin, “Endurance enhancement of multi-level cell phase change memory,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2019.paper
Yonghwi Kwon, Inhak Han, and Youngsoo Shin, “Clock gating synthesis of netlist with cyclic logic paths,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2019.paper
Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, and Youngsoo Shin, “Cut optimization for redundant via insertion in self-aligned double patterning,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 6, pp. 61:1-61:21, Sep. 2019. paper
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Neural network classifier-based OPC with imbalanced training data,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 38, no. 5, pp. 938-948, May 2019. paper
Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Standard cell layout design and placement optimization for TFET-based circuits,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May 2019.paper
Daijoon Hyun, Yuepeng Fan, and Youngsoo Shin, “Accurate wirelength prediction for placement-aware synthesis through machine learning,” Proc. Design, Automation & Test in Europe (DATE), pp. 324-327, Mar. 2019.paper
Jinwook Jung, Gi-Joon Nam, Woohyun Chung, and Youngsoo Shin, “Integrated latch placement and cloning for timing optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 2, pp. 22:1-22:17, Feb. 2019. paper
Daijoon Hyun and Youngsoo Shin, “Integrated approach of airgap insertion for circuit timing optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 2, pp. 24:1-24:22, Feb. 2019. paper
Yonghwi Kwon, Youngsoo Song, and Youngsoo Shin, “Optical proximity correction using bidirectional recurrent neural network (BRNN),” Proc. SPIE Advanced Lithography, Feb. 2019.paper

2018

Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, “OWARU: free space-aware timing-driven incremental placement with critical path smoothing,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 37, no. 9, pp. 1825-1838, Sep. 2018. paper
Inhak Han and Youngsoo Shin, “Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops,” ACM Transactions on Design Automation of Electronic Systems, vol. 23, no. 5, pp. 61:1-61:21, Aug. 2018. paper
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Electrothermal analysis with non-convective boundary conditions,” IEEE Transactions on Circuits and Systems II, vol. 65, no. 8, pp. 1044-1048, Aug. 2018. paper
Joonhyuk Cho, Gangmin Cho, and Youngsoo Shin, “Optimization of machine learning guided optical proximity correction,” Proc. Int’l Midwest Symp. on Circuits and Systems (MWSCAS), pp. 921-924, Aug. 2018. paper
Kiwon Yoon, Daijoon Hyun, and Youngsoo Shin, “Fast timing analysis of non-tree clock network with shorted wires,” Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 279-284, May 2018.paper
Yonghwi Kwon, Jinwook Jung, Inhak Han, and Youngsoo Shin, “Transient clock power estimation of pre-CTS netlist,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May 2018.paper
Daijoon Hyun, Jaewoo Seo, and Youngsoo Shin, “Library optimization for near threshold voltage design,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May 2018.paper
Jingon Lee, Jinwook Jung, and Youngsoo Shin, “Fast timing analysis of transistor-level full custom digital circuits,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), May 2018.paper
Yeongmin Lee, Min-Gyu Park, Youngbae Hwang, Youngsoo Shin, and Chong-Min Kyung, “Memory-efficient parametric semi-global matching,” IEEE Signal Processing Letters, vol. 25, no. 2, pp. 194-198, Feb. 2018. paper
Jaewoo Seo, Jinwook Jung, and Youngsoo Shin, “A compact multi-bit flip-flop with smaller height implementation and metal-less clock routing,” Proc. SPIE Advanced Lithography, pp. 1-9 (105880A), Feb. 2018.paper
Youngsoo Song, Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Timing optimization in SADP process through wire widening and double via insertion,” Proc. SPIE Advanced Lithography, pp. 1-7, Feb. 2018.paper
Sangmin Kim and Youngsoo Shin, “Module grouping to reduce the area of test wrappers in SoCs,” Integration, the VLSI Journal, vol. 60, pp. 39-47, Jan. 2018. paper
Daijoon Hyun and Youngsoo Shin, “Automatic insertion of airgap with design rule constraints,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 381-386, Jan. 2018.paper

2017

Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant via insertion in SADP process with cut merging and optimization,” Proc. Int’l Conf. on Very Large Scale Integration (VLSI-SoC), pp. 1-6, Oct. 2017. (Invited Paper)paper
Seongbo Shim and Youngsoo Shin, “Fast verification of guide patterns for directed self-assembly lithography,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 36, no. 9, pp. 1522-1531, Sep. 2017. paper
Jaewoo Seo, Jinwook Jung, Sangmin Kim, and Youngsoo Shin, “Pin accessibility-driven cell layout redesign and placement optimization,” Proc. Design Automation Conf. (DAC), pp. 54:1-54:6, June 2017.paper
Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant via insertion with cut optimization for self-aligned double patterning,” Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 137-142, May 2017.paper
Youngsoo Song, Sangmin Kim, and Youngsoo Shin, “Timing-aware wire width optimization for SADP process,” Proc. Design, Automation & Test in Europe (DATE), pp. 1639-1642, Mar. 2017. paper
Wachirawit Ponghiran, Seongbo Shim, and Youngsoo Shin, “Cut mask optimization for multi-patterning directed self-assembly lithography,” Proc. Design, Automation & Test in Europe (DATE), pp. 1498-1503, Mar. 2017. paper
Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin, “Clock tree optimization through selective airgap insertion,” Proc. Int’l Symp. on Quality Electronic Design (ISQED), pp. 203-208, Mar. 2017. paper
Seongbo Shim and Youngsoo Shin, “Machine learning-guided etch proximity correction,” IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 1, pp. 1-7, Feb. 2017. paper
Jaewoo Seo and Youngsoo Shin, “Routability enhancement through unidirectional standard cells with floating metal-2,” Proc. SPIE Advanced Lithography, pp. 1-8 (101480K), Feb. 2017. paper
Daijoon Hyun and Youngsoo Shin, “Selection of airgap layers for circuit timing optimization,” Proc. SPIE Advanced Lithography, pp. 1-8 (101480O), Feb. 2017. paper
Youngsoo Song, Jinwook Jung, and Youngsoo Shin, “Redundant via insertion in self-aligned double patterning,” Proc. SPIE Advanced Lithography, pp. 1-8 (1014806), Feb. 2017. paper
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, “Machine learning-based resist 3D model,” Proc. SPIE Advanced Lithography, pp. 1-10 (101471D), Feb. 2017. paper
Suhyeong Choi, Jae Uk Lee, Victor Blanco, Ryoung-Han Kim, and Youngsoo Shin, “2D self-aligned via patterning strategy with EUV single exposure in 3nm technology,” Proc. SPIE Advanced Lithography, pp. 1-8 (1014321), Feb. 2017. paper
Suhyeong Choi, Jae Uk Lee, Victor Blanco, Peter Debacker, Praveen Raghavan, Ryoung-Han Kim, and Youngsoo Shin, “Large marginal 2D self-aligned via patterning for sub-5nm technology,” Proc. SPIE Advanced Lithography, pp. 1-10 (101480J), Feb. 2017. paper
Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Lithography defect probability and its application to physical design optimization,” IEEE Transactions on Very Large Scale Integration Systems, vol. 25, no. 1, pp. 271-285, Jan. 2017. paper

2016

Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, “OWARU: free space-aware timing-driven incremental placement,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 8:1–8:8, Nov. 2016. paper
Sangmin Kim, Ik Joon Chang, and Youngsoo Shin, “Synthesis of dual-mode circuits through optimizing transition time constraints,” Proc. Int’l Conf. on Consumer Electronics, pp. 97-99, Oct. 2016. paper
Byoung Kuk You, Jong Min Kim, Daniel J. Joe, Kyounghoon Yang, Youngsoo Shin, Yeon Sik Jung, and Keon Jae Lee, “Reliable memristive switching memory devices enabled by densely packed silver nanocone arrays as electric-field concentrators,” ACS Nano, 10(10), pp. 9478-9488, Oct. 2016. paper
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, “Machine learning (ML)-based lithography optimizations,” Proc. Asia Pacific Conf. on Circuits and Systems (APCCAS), pp. 530-533, Oct. 2016. (Invited Paper)paper
Kiwon Yoon, Suhyeong Choi, and Youngsoo Shin, “Area efficient neuromorphic circuit based on stochastic computation,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 73-74, Oct. 2016.paper
Jinwook Jung and Youngsoo Shin, “Localized DNA circuit design with majority gates,” Proc. BioMedical Circuits and Systems Conf., pp. 172–175, Oct. 2016.paper
Inhak Han, Jonggyu Kim, Joonhwan Yi, and Youngsoo Shin, “Register grouping for synthesis of clock gating logic,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), June 2016.paper
Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Placement optimization for MP-DSAL compliant layout,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), June 2016. (Invited Paper)paper
Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Redundant via insertion for multiple-patterning directed-self-assembly lithography,” Proc. Design Automation Conf. (DAC), pp. 41:1-41:6 June 2016.paper
Sangmin Kim, Seokhyeong Kang, and Youngsoo Shin, “Synthesis of dual-mode circuits through library design, gate sizing, and clock tree optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 21, no.3, pp. 51, May 2016. paper
Kiwon Yoon, Seongbo Shim, and Youngsoo Shin, “Crosslink insertion for minimizing OCV clock skew,” Proc. Int’l Symp. on Circuits and Systems (ISCAS), pp. 2587-2590, May 2016.paper
Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, and Youngsoo Shin, “Wakeup scheduling and its buffered tree synthesis for power gating circuits,” Integration, the VLSI Journal, vol. 53, pp. 157-170, Mar. 2016. paper
Woohyun Chung, Seongbo Shim, and Youngsoo Shin, “Redundant via insertion in directed self-assembly lithography,” Proc. Design, Automation & Test in Europe (DATE), pp. 55-60, Mar. 2016.paper
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, “Light interference map: a prescriptive optimization of lithography-friendly layout,” IEEE Transactions on Semiconductor Manufacturing, vol. 29, pp.44-49, Feb. 2016. paper
Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, and Youngsoo Shin, “One-cycle correction of timing errors in pipelines with standard clocked elements,” IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 2, pp. 600-612, Feb. 2016. paper
Daijoon Hyun and Youngsoo Shin, “Modeling interconnect corners under double patterning misalignment,” Proc. SPIE Advanced Lithography, pp. 97810F-97810F-7, Feb. 2016. paper
Youngsoo Song, Jeemyung Lee, Seongmin Lee and Youngsoo Shin, “Integrated routing and fill for self-aligned double patterning (SADP) using grid-based design,” Proc. SPIE Advanced Lithography, pp. 978105-978105-8, Feb. 2016. paper
Seongbo Shim and Youngsoo Shin, “Etch proximity correction through machine-learning-driven etch bias model,” Proc. SPIE Advanced Lithography, pp. 97820O-97820O-10, Feb. 2016. paper
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Machine learning (ML)-guided OPC using basis functions of polar Fourier transform,” Proc. SPIE Advanced Lithography, pp. 97800H-97800H-8, Feb. 2016. paper
Seongbo Shim and Youngsoo Shin, “Mask optimization for directed self-assembly lithography: inverse DSA and inverse lithography,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp.83-88, Jan. 2016. paper
Inhak Han, Daijoon Hyun, and Youngsoo Shin, “Buffer insertion to remove hold violations at multiple process corners,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 232-237, Jan. 2016. paper

2015

Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Defect probability of directed self-assembly lithography: fast identification and post-placement optimization,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 404-409, Nov. 2015. paper
Daijoon Hyun and Youngsoo Shin, “Calibration of interconnect corners using on-chip ring oscillators,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 141-142, Nov. 2015. (Best Paper Award) paper
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, “Electrothermal analysis with generalized boundary conditions,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 39-40, Nov. 2015. paper
Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, “Physical synthesis of DNA circuits with spatially localized gates,” Proc. Int’l Conf. on Computer Design (ICCD), pp. 280-286, Oct. 2015. paper
Seongbo Shim and Youngsoo Shin, “Physical design and mask optimization for directed self-assembly lithography (DSAL),” Proc. Int’l Conf. on Very Large Scale Integration (VLSI-SoC), pp. 80-85, Oct. 2015. paper
Seongbo Shim, Jae Wook Lee, and Youngsoo Shin, “An analytical approach to thermal design and optimization with a temperature-dependent power model,” IEEE Transactions on Circuits and Systems I, vol. 62, no. 3, pp. 816-824, Mar. 2015. paper
Woohyun Chung, Seongbo Shim, and Youngsoo Shin, “Identifying redundant inter-cell margins and its application to reducing routing congestion,” Proc. Design, Automation & Test in Europe (DATE), pp. 1659-1664, Mar. 2015. paper
Seongbo Shim, Sibo Cai, Jaewon Yang, Seunghune Yang, Byungil Choi, and Youngsoo Shin, “Verification of direct self-assembly (DSA) guide patterns through machine learning,” Proc. SPIE Advanced Lithography, pp. 94231E-94231E-8, Mar. 2015. paper
Insup Shin, Jae-Joon Kim, and Youngsoo Shin, “Aggressive voltage scaling through fast correction of multiple errors with seamless pipeline operation,” IEEE Transactions on Circuits and Systems I, vol. 62, no. 2, pp. 468-477, Feb. 2015. paper
Seongbo Shim and Youngsoo Shin, “Topology-oriented pattern extraction and classification for synthesizing lithography test patterns,” Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 14(1), no. 013503, pp. 1-12, Jan. 2015. paper

2014

Jinwook Jung, Dongsoo Lee, and Youngsoo Shin, “Design and optimization of multiple-mesh clock network,” Proc. Int’l Conf. on Very Large Scale Integration (VLSI-SoC), pp. 171-176, Oct. 2014. paper
Inhak Han and Youngsoo Shin, “Simplifying clock gating logic by matching factored forms,” IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 6, pp. 1338-1349, June 2014. paper
Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Synthesis of lithography test patterns through topology-oriented pattern extraction and classification,” Proc. SPIE Advanced Lithography, pp. 1-10 (905305), Feb. 2014. paper
Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, and Seungwhun Paik, “HAPL: heterogeneous array of programmable logic using selective mask patterning,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 1, pp. 146-159, Jan. 2014. paper
Seongbo Shim, Yoojong Lee, and Youngsoo Shin, “Lithographic defect aware placement using compact standard cells without inter-cell margin,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 47-52, Jan. 2014. paper
Insup Shin, Jae-Joon Kim, and Youngsoo Shin, “Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 179-184, Jan. 2014. paper

2013

Yongsoo Ahn, Donkyu Baek, Dongsoo Lee, and Youngsoo Shin, “Pulsed-Vdd: synchronous circuit design without clock network,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 192-193, Nov. 2013.paper
Seongbo Shim, Minyoung Mo, Sangmin Kim, and Youngsoo Shin, “Analysis and minimization of short-circuit current in mesh clock network,” Proc. Int’l Conf. on Computer Design (ICCD), pp. 459-462, Oct. 2013. paper
Donkyu Baek, Insup Shin, and Youngsoo Shin, “Accurate gate delay extraction for timing analysis of body-biased circuits,” Journal of Circuits, Systems, and Computers, vol. 22, no. 8, Sep. 2013.paper
Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, and Youngsoo Shin, “A pipeline architecture with 1-cycle timing error correction for low voltage operations,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), pp. 199-204, Sep. 2013. paper
Inhak Han and Youngsoo Shin, “Folded circuit synthesis: logic simplification using dual edge-triggered flip-flops,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), pp. 17-20, May 2013. paper
Sangmin Kim, Duckhwan Kim, and Youngsoo Shin, “Pulsed-latch ASIC synthesis in industrial design flow,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 356-361, Jan. 2013. paper

2012

Insup Shin, Donkyu Baek, and Youngsoo Shin, “Introducing irregularity to routing architecture of structured ASIC for better routability,” Proc. Int’l Conf. on Field-Programmable Technology (FPT), pp. 224-228, Dec. 2012. paper
Nam Sung Kim, Abhishek Sinkar, Jun Seomun, and Youngsoo Shin, “Maximizing frequency and yield of power-constrained designs using programmable power-gating,” IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 10, pp. 1885-1890, Oct. 2012.paper
Seungwhun Paik, Inhak Han, Sangmin Kim, and Youngsoo Shin, “Clock gating synthesis of pulsed-latch circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 7, pp. 1019-1030, July 2012.paper
Donkyu Baek, Insup Shin, and Youngsoo Shin, “Gate delay modeling for static timing analysis of body-biased circuits,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), May 2012. paper
Inhak Han and Youngsoo Shin, “Synthesis of clock gating logic through factored form matching,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), May 2012. paper
Insup Shin, Seungwhun Paik, Dongwan Shin, and Youngsoo Shin, “HLS-dv: a high-level synthesis framework for dual-Vdd architectures,” IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 4, pp. 593-604, Apr. 2012.paper
Jun Seomun, Insup Shin, and Youngsoo Shin, “Synthesis of active-mode power-gating circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 3, pp. 391-403, Mar. 2012.paper

2011

Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, and Youngsoo Shin, “Sampling correlation sources for timing yield analysis of sequential circuits with clock networks,” Journal of Circuits, Systems, and Computers, vol. 20, no. 8, pp. 1547-1569, Dec. 2011.paper
Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, and Yao-Wen Chang, “Pulsed-latch aware placement for timing-integrity optimization,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 30, no. 12, pp. 1856-1869, Dec. 2011.paper
Youngsoo Shin and Seungwhun Paik, “Pulsed-latch circuits: a new dimension in ASIC design,” IEEE Design & Test of Computers, vol. 28, no. 6, pp. 50-57, Nov./Dec. 2011.paper
Jaeha Kung and Youngsoo Shin, “Compact thermal models: assessment and pitfalls,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 337-340, Nov. 2011. (Invited Paper)paper
Seungwhun Paik, Gi-Joon Nam, and Youngsoo Shin, “Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 640-646, Nov. 2011. paper
Seungwhun Paik, Seonggwan Lee, and Youngsoo Shin, “Retiming pulsed-latch circuits with regulating pulse width,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 30, no. 8, pp. 1114-1127, Aug. 2011.paper
Seungwhun Paik, Jaeha Kung, and Youngsoo Shin, “Exploring the opportunity of optimizing sequencing elements in ASIC designs,” Proc. Int’l Midwest Symp. on Circuits and Systems (MWSCAS), pp. 394-397, Aug. 2011. (Invited Paper)paper
Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, and Youngsoo Shin, “Thermal signature: a simple yet accurate thermal index for floorplan optimization,” Proc. Design Automation Conf. (DAC), pp. 108-113, June 2011. paper
Jun Seomun and Youngsoo Shin, “Design and optimization of power-gated circuits with autonomous data-retention,” IEEE Transactions on Very Large Scale Integration Systems, vol. 19, no. 2, pp. 227-236, Feb. 2011.paper
Donkyu Baek, Insup Shin, Seungwhun Paik, and Youngsoo Shin, “Selectively patterned masks: structured ASIC with asymptotically ASIC performance,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 376-381, Jan. 2011. paper
Sangmin Kim, Inhak Han, Seungwhun Paik, and Youngsoo Shin, “Pulser gating: a clock gating of pulsed-latch circuits,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 190-195, Jan. 2011. paper

2010

Byunghee Choi and Youngsoo Shin, “Lookup table-based adaptive body biasing of multiple macros for process variation compensation and low leakage,” Journal of Circuits, Systems, and Computers, vol. 19, no. 7, pp. 1449-1464, Nov. 2010.paper
Donkyu Baek, Insup Shin, Seungwhun Paik, and Youngsoo Shin, “Selectively patterned masks: beyond structured ASIC,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 154-157, Nov. 2010. (Invited Paper)paper
Seungwhun Paik and Youngsoo Shin, “Pulsed-latch circuits to push the envelope of ASIC design,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 150-153, Nov. 2010. (Invited Paper)paper
Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, and Takayasu Sakurai, “Power gating: circuits, design methodologies, and best practice for standard-cell VLSI designs,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 4, article 28, pp. 28:1-28:37, Sep. 2010. (Top 10 most downloaded ACM TODAES articles published in 2010)paper
Seungwhun Paik, Sangmin Kim, and Youngsoo Shin, “Wakeup synthesis and its buffered tree construction for power gating circuit designs,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), pp. 413-418, Aug. 2010. paper
Jun Seomun, Insup Shin, and Youngsoo Shin, “Synthesis and implementation of active mode power gating circuits,” Proc. Design Automation Conf. (DAC), pp. 487-492, June 2010. paper
Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, and Yao-Wen Chang, “Pulsed-latch-aware placement for timing-integrity optimization,” Proc. Design Automation Conf. (DAC), pp. 280-285, June 2010. paper
Inhak Han, Lee-eun Yu, and Youngsoo Shin, “Fast Monte Carlo method via reduced sample number and node filtering,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), pp. 126-129, June 2010. paper
Seungwhun Paik, Insup Shin, Taewhan Kim, and Youngsoo Shin, “HLS-l: a high-level synthesis framework for latch-based architectures,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 5, pp. 657-670, May 2010paper
Hyein Lee, Seungwhun Paik, and Youngsoo Shin, “Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 3, pp. 355-366, Mar. 2010. (Top 25 most downloaded articles for IEEE TCAD in 2010)paper
Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, and Youngsoo Shin, “Supply switching with ground collapse for low-leakage register files in 65-nm CMOS,” IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 3, pp. 505-509, Mar. 2010.paper
Seungwhun Paik, Lee-eun Yu, and Youngsoo Shin, “Statistical time borrowing for pulsed-latch circuit designs,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 675-680, Jan. 2010. paper
Jun Seomun, Seungwhun Paik, and Youngsoo Shin, “Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 581-586, Jan. 2010. paper

2009

Jaehyun Kim, Chungki Oh, and Youngsoo Shin, “Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 1, article 4, pp. 4:1-4:22, Dec. 2009.paper
Jun Seomun and Youngsoo Shin, “Self-retention of data in power-gated circuits,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 212-215, Nov. 2009. (Invited Paper)paper
Seonggwan Lee, Seungwhun Paik, and Youngsoo Shin, “Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 375-380, Nov. 2009.paper
Nam Sung Kim, Jun Seomun, Abhishek Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, and Youngsoo Shin, “Frequency and yield optimization using power gates in power-constrained designs,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), pp. 121-126, Aug. 2009.paper
Insup Shin, Seungwhun Paik, and Youngsoo Shin, “Register allocation for high-level synthesis using dual supply voltages,” Proc. Design Automation Conf. (DAC), pp. 937-942, July 2009.paper
Lee-eun Yu, Changsik Shin, Jing-Jia Liou, and Youngsoo Shin, “Timing yield estimation with clock network correlations by propagating discrete probability distributions,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), pp. 63-66, May 2009.paper
Chungki Oh, Sangmin Kim, and Youngsoo Shin, “Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating,” Proc. Int’l Conf. on IC Design & Technology (ICICDT), pp. 59-62, May 2009.paper
Seungwhun Paik, Insup Shin, and Youngsoo Shin, “HLS-l: high-level synthesis of high performance latch-based circuits,” Proc. Design, Automation & Test in Europe (DATE), pp. 1112-1117, Apr. 2009.paper
Eunjoo Choi, Changsik Shin, and Youngsoo Shin, “HLS-pg: high-level synthesis of power-gated circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 28, no. 3, pp. 451-456, Mar. 2009.paper
Youngsoo Shin, Seungwhun Paik, and Hyung-Ock Kim, “Semicustom design of zigzag power-gated circuits in standard cell elements,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 28, no. 3, pp. 327-339, Mar. 2009.paper

2008

Jun Seomun, Jae-hyun Kim, and Youngsoo Shin, “Skewed flip-flop and mixed-Vt gates for minimizing leakage in sequential circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 27, no. 11, pp. 1956-1968, Nov. 2008.paper
Hyein Lee, Seungwhun Paik, and Youngsoo Shin, “Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 224-229, Nov. 2008.paper
Eunjoo Choi, Changsik Shin, Taewhan Kim, and Youngsoo Shin, “Power-gating-aware high-level synthesis,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), pp. 39-44, Aug. 2008.paper
Seungwhun Paik and Youngsoo Shin, “Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements,” Proc. Design Automation Conf. (DAC), pp. 600-605, June 2008.paper
Eunjoo Choi and Youngsoo Shin, “3-D thermal simulation with dynamic power profiles,” Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), pp. 2765-2769, May 2008.paper
Jinseob Jeong, Seungwhun Paik, and Youngsoo Shin, “Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 629-634, Jan. 2008.paper

2007

Sewan Heo and Youngsoo Shin, “Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping,” Journal of Semiconductor Technology and Science, vol.7, no.4, pp. 215-220, Dec. 2007.paper
Sewan Heo and Youngsoo Shin, “Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping,” Proc. Int’l SoC Design Conf. (ISOCC), Oct. 2007.paper
Jae-hyun Kim and Youngsoo Shin, “Minimizing leakage power in sequential circuits by using mixed Vt flip-flops,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 797-802, Nov. 2007.paper
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, and Jung Yun Choi, “Supply switching with ground collapse: simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits,” IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 7, pp. 758-766, July 2007. paper
Hyung-Ock Kim and Youngsoo Shin, “Semicustom design methodology of power gated circuits for low leakage applications,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 6, pp. 512-516, June 2007.paper
Jun Seomun, Jae-hyun Kim, and Youngsoo Shin, “Skewed flip-flop transformation for minimizing leakage in sequential circuits,” Proc. Design Automation Conf. (DAC), pp. 103-106, June 2007.paper
Youngsoo Shin and Hyung-Ock Kim, “Cell-based semicustom design of zigzag power gating circuits,” Proc. Int’l Symp. on Quality Electronic Design (ISQED), pp. 527-532, Mar. 2007.paper
Byunghee Choi and Youngsoo Shin, “Lookup table-based adaptive body biasing of multiple macros,” Proc. Int’l Symp. on Quality Electronic Design (ISQED), pp. 533-538, Mar. 2007. (Nominated for Best Paper Award)paper
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, and Jung Yun Choi, “Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 654-659, Jan. 2007.paper

2006

Byunghee Choi and Youngsoo Shin, “Fine-grain control of multiple functional blocks with lookup table-based adaptive body biasing,” Proc. Int’l SoC Design Conf. (ISOCC), pp. 357-360, Oct. 2006 (Best Paper Award)paper
Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, and Iksoo Eo, “Physical design methodology of power gating circuits for standard-cell-based design,” Proc. Design Automation Conf. (DAC), pp. 109-112, July 2006.paper
Youngsoo Shin and Junghyup Lee, “Power analysis of VLSI interconnect with RLC tree models and model reduction,” Journal of Circuits, Systems, and Computers, vol. 15, no. 3, pp.399-408, June 2006.paper
Sewan Heo, Hyung-Ock Kim, and Youngsoo Shin, “Power gating and supply control for low standby leakage power of VLSI circuits,” Proc. Symp. on Low-Power and High-Speed Chips (COOL Chips), pp. 305-307, Apr. 2006.paper
Hyung-Ock Kim and Youngsoo Shin, “Analysis and optimization of gate leakage current of power gating circuits,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 565-569, Jan. 2006.paper

2005

Hyung-Ock Kim and Youngsoo Shin, “Power-aware slack distribution for hierarchical VLSI design,” Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), pp. 4150-4153, May 2005. paper
Youngsoo Shin and Hyung-Ock Kim, “Analysis of power consumption in VLSI global interconnects,” Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), pp. 4713-4716, May 2005. paper
Subhrajit Bhattacharya, John Darringer, Daniel Ostapko, and Youngsoo Shin, “A mask reuse methodology for reducing System-on-a-Chip cost,” Proc. Int’l Symp. on Quality Electronic Design (ISQED), pp. 482-487, Mar. 2005. (Best Paper Award)paper
Hiroshi Kawaguchi, Youngsoo Shin, and Takayasu Sakurai, “uITRON-LP: power conscious real-time OS based on cooperative voltage scaling for multimedia applications,” IEEE Transactions on Multimedia, vol. 7, no. 1, pp. 177-185, Feb. 2005. (Corresponding project received LSI IP Design Award in 2002) paper

2004

Nagu Dhanwada, Reinaldo A. Bergamaschi, William Dungan, Indira I. Nair, William E. Dougherty, Youngsoo Shin, Subhrajit Bhattacharya, Ing-Chao Lin, John Darringer, and Sarala Paliwal, “Simultaneous exploration of power, physical design, and architectural performance dimensions of SoC design space using SEAS,” Proc. IP Based SoC Design Forum & Exhibition (IP-SoC), Dec. 2004. paper
Jingcao Hu, Youngsoo Shin, Nagu Dhanwada, and Radu Marculescu, “Architecting voltage islands in core-based System-on-a-Chip designs,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), pp. 180-185, Aug. 2004. paper
Dan Knebel, Stephen Kosonocky, Subhrajit Bhattacharya, Ruchir Puri, and Youngsoo Shin, “Leakage control through fine-grained power gating: methodology and implementation,” Proc. IBM Austin Conf. on Energy-Efficient Design (ACEED), Mar. 2004.

2003

Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira I. Nair, John Darringer, and Sarala Paliwal, “SEAS: a system for early analysis of SoCs,” Proc. Int’l Conf. on Hardware/Software Codesign and System Synthesis, pp. 150-155, Oct. 2003. paper
Indira I. Nair, Youngsoo Shin, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, John Darringer, and Stephen Kosonocky, “Modeling and analysis of power for System-on-a-Chip design,” Proc. IBM Austin Conf. on Energy-Efficient Design (ACEED), Mar. 2003.

2002

John Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira I. Nair, Patricia Sagmeister, and Youngsoo Shin, “Early analysis tools for System-on-a-Chip design,” IBM Journal of Research and Development, vol. 46, no. 6, pp. 691-707, Nov. 2002.paper
S. Kim, Youngsoo Shin, Stephen Kosonocky, and W. Hwang, “Long-term power minimization of dual-Vt CMOS circuits,” Proc. Int’l ASIC/SOC Conf., pp. 323-327, Sep. 2002.paper
Youngsoo Shin and Takayasu Sakurai, “Power distribution analysis of VLSI interconnects using model order reduction,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 21, no. 6, pp. 739-745, June 2002.paper
Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Youngsoo Shin, and Takayasu Sakurai, “A controller LSI for realizing Vdd-hopping scheme with off-the-shelf processors and its application to MPEG4 system,” IEICE Transactions on Electronics, vol. E58-C, no. 2, pp. 263-271, Feb. 2002.paper

2001

Youngsoo Shin, Kiyoung Choi, and Young-Hoon Chang, “Narrow bus encoding for low-power DSP systems,” IEEE Transactions on Very Large Scale Integration Systems, vol. 9, no. 5, pp. 656-660, Oct. 2001.paper
Youngsoo Shin and Takayasu Sakurai, “Estimation of power distribution in VLSI interconnects,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), pp. 370-375, Aug. 2001. paper
Youngsoo Shin and Takayasu Sakurai, “Coupling-driven bus design for low-power application-specific systems,” Proc. Design Automation Conf. (DAC), pp. 750-753, June 2001. paper
Hiroshi Kawaguchi, Youngsoo Shin, and Takayasu Sakurai, “Experimental evaluation of cooperative voltage scaling (CVS): a case study,” Proc. IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp. 17-23, May 2001. paper
Youngsoo Shin, Hiroshi Kawaguchi, and Takayasu Sakurai, “Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems,” Proc. Custom Integrated Circuits Conf. (CICC), pp. 553-556, May 2001. paper
Youngsoo Shin, Kiyoung Choi, and Takayasu Sakurai, “Power-conscious scheduling for real-time embedded systems design,” VLSI Design: An Int’l Journal of Custom-Chip Design, Simulation, and Testing, vol. 12, no. 2, pp. 139-150, 2001.paper
Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, “Partial bus-invert coding for power optimization of application-specific systems,” IEEE Transactions on Very Large Scale Integration Systems, vol. 9, no. 2, pp. 377-383, Apr. 2001.paper

2000

Youngsoo Shin, Kiyoung Choi, and Takayasu Sakurai, “Power optimization of real-time embedded systems on variable speed processors,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 365-368, Nov. 2000. paper
Youngsoo Shin, Daehong Kim, and Kiyoung Choi, “Schedulability-driven performance analysis of multiple mode embedded real-time systems,” Proc. Design Automation Conf. (DAC), pp. 495-500, June 2000. paper
Youngsoo Shin and Kiyoung Choi, “Narrow bus encoding for low power systems,” Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 217-220, Jan. 2000. paper

1999

Youngsoo Shin and Kiyoung Choi, “Power conscious fixed priority scheduling for hard real-time systems,” Proc. Design Automation Conf. (DAC), pp. 134-139, June 1999. paper

1998

Youngsoo Shin and Kiyoung Choi, “Rate assignment for embedded reactive real-time systems,” Proc. Euromicro Workshop on Digital Systems Design, pp. 237-242, Aug. 1998.
Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, “Partial bus-invert coding for power optimization of system level bus,” Proc. Int’l Symp. on Low Power Electronics and Design (ISLPED), pp. 127-129, Aug. 1998. paper
Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, “Reduction of bus transitions with partial bus-invert coding,” IEE Electronics Letters, vol. 34, no. 7, pp. 642-643, Apr. 1998.paper
Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, and Kiyoung Choi, “An integrated cosimulation environment for heterogeneous systems prototyping,” Design Automation for Embedded Systems, vol. 3, issue 2/3, pp. 163-186, Mar. 1998, Kluwer Academic Publishers.paper

1997

Youngsoo Shin and Kiyoung Choi, “Enhancing schedulability of hard real-time systems through codesign,” Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), pp. 1576-1579, June 1997.
Youngsoo Shin and Kiyoung Choi, “Enforcing schedulability of multi-task systems by hardware-software codesign,” Proc. 5th Int’l Workshop on Hardware/Software Co-Design (Codes/CASHE), pp. 3-7, Mar. 1997. paper

1996

Youngsoo Shin and Kiyoung Choi, “Software synthesis through task decomposition by dependency analysis,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), pp. 98-102, Nov. 1996. paper
Kyuseok Kim, Yongjoo Kim, Youngsoo Shin, and Kiyoung Choi, “An integrated hardware-software cosimulation environment with automated interface generation,” Proc. 7th IEEE Int’l Workshop on Rapid Systems Prototyping, pp. 66-71, June 1996.
Youngsoo Shin and Kiyoung Choi, “Thread-based software synthesis for embedded system design,” Proc. European Design & Test Conf. (ED&TC), pp. 282-286, Mar. 1996.

1995

Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, and Soonhoi Ha, “An integrated hardware-software cosimulation environment for heterogeneous systems prototyping,” Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), pp. 101-106, Aug. 1995.
Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jaehee Won, and Kiyoung Choi, “Efficient prototyping system based on incremental design and module-by-module verification,” Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), pp. 924-927, Apr. 1995.
Note Many of the papers above have been made available for easy access. Please be aware that they are copyrighted by the organization responsible for the corresponding conference or journal.

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