Design Technology Lab

DT LAB   →  M.S. Candidates   →  Youngjin Chae (채영진)

Youngjin Chae (채영진)

M.S. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering M.S. (Sep. 2025 – Present)
  • Korea University, School of Electrical Engineering B.S. (Mar. 2021 – Feb. 2025)
  • Jeonnam Science High School (Mar. 2018 – Feb. 2021)

Research Interests

  • Design technology co-optimization

Experiences

Honors

Publications

Journal Papers

Conference Papers

  1. Seohyun Kim, Youngjin Chae, Shilong Zhang, and Youngsoo Shin, “Clock distribution network with backside clock mesh in BSPDN architecture,” Proc. IEEE/JSAP Symp. on VLSI Technology & Circuits, submitted.
  2. Seohyun Kim, Shilong Zhang, Youngjin Chae, and Youngsoo Shin, “Header sizing and placement for power-gating with backside PDN,” Proc. Design Automation Conf. (DAC), submitted.
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