Design Technology Lab

DT LAB   →  M.S. Candidates   →  Soyoon Choi (최소윤)

Soyoon Choi (최소윤)

M.S. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering M.S. (Mar. 2023 – Present)
  • Sungkyunkwan University, School of Electronic & Electrical Engineering B.S. (Mar. 2018 – Feb. 2023)
  • Hyundai Chung-Un High School (Mar. 2015 – Feb. 2018)

Research Interests

  • Design methodology for 3D IC

Honors

Publications

Journal Papers

Conference Papers

  1. Younggwang Jung, Daijoon Hyun, Soyoon Choi, and Youngsoo Shin, “Power distribution network optimization using HLA-GCN for routability enhancement,” Proc. Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2023.
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