Design Technology Lab

DT LAB   →  M.S. Candidates   →  Jaeheon Kim (김재헌)

Jaeheon Kim (김재헌)

M.S. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering M.S. (Mar. 2023 – Present)
  • Korea University, School of Electrical Engineering B.S. (Mar. 2017 – Feb. 2023)
  • Gumi High School (Mar. 2014 – Feb. 2017)

Research Interests

  • Design methodology for processing-in-memory (PIM)

Honors

Publications

Journal Papers

Conference Papers

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