Design Technology Lab

DT LAB   →  M.S. Candidates   →  Geuna Chang (장근아)

Geuna Chang (장근아)

M.S. candidate, School of EE, KAIST
  • location
    291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
  • Office
    School of Electrical Engineering (E3-2), 5219

Education

  • KAIST, School of Electrical Engineering M.S. (Mar. 2024 – Present)
  • Ewha Womans University, School of Electronic & Electrical Engineering B.S. (Mar. 2020 – Feb. 2024)
  • Gimpo High School (Mar. 2016 – Feb. 2019)

Research Interests

Experiences

Honors

Publications

Journal Papers

Conference Papers

  1. Geuna Chang, Shilong Zhang, Seohyun Kim, Woojin Kim, and Youngsoo Shin, “Verilog code generation of hierarchical design using LLMs,” Proc. Int’l Symp. on Machine Learning for CAD (MLCAD), accepted.
  2. Minseung Shin, Shilong Zhang, Geuna Chang, and Youngsoo Shin, “On-chip decoupling capacitor placement with impedance constraint for DRAM design,” Proc. Int’l Symp. on Machine Learning for CAD (MLCAD), accepted.
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