Geuna Chang (장근아)
Ph.D. candidate, School of EE, KAIST
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location291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
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OfficeSchool of Electrical Engineering (E3-2), 5219
Education
- KAIST, School of Electrical Engineering Ph.D. (Mar. 2026 – Present)
- KAIST, School of Electrical Engineering M.S. (Mar. 2024 – Feb. 2026)
- Ewha Womans University, School of Electronic & Electrical Engineering B.S. (Mar. 2020 – Feb. 2024)
- Gimpo High School (Mar. 2016 – Feb. 2019)
Research Interests
Experiences
Honors
Publications
Journal Papers
- Min Kim, Shilong Zhang, Geuna Chang, and Youngsoo Shin, “Shield-aware routing for signal integrity compliance in high-speed UCIe chiplet interconnects,” IEEE Electromagnetic Compatibility Magazine, submitted.
Conference Papers
- Geuna Chang, Sohee Son, Min Kim, and Youngsoo Shin, “Post-synthesis clock-constraint repair using LLM agent,” Proc. Design, Automation & Test in Europe (DATE), submitted.
- Geuna Chang, Seohyun Kim, and Youngsoo Shin, “Automated RTL refinement using LLMs: a case study in clock gating,” Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), accepted. (Invited)
- Min Kim, Shilong Zhang, Geuna Chang, and Youngsoo Shin, “Signal-integrity-aware routing and shielding for UCIe-compliant 2.5D ICs,” Proc. Workshop on Signal and Power Integrity (SPI), Jun. 2026.
- Geuna Chang, Shilong Zhang, Seohyun Kim, Woojin Kim, and Youngsoo Shin, “Verilog code generation of hierarchical design using LLMs,” Proc. Int’l Symp. on Machine Learning for CAD (MLCAD), Sep. 2025
- Minseung Shin, Shilong Zhang, Geuna Chang, and Youngsoo Shin, “On-chip decoupling capacitor placement with impedance constraint for DRAM design,” Proc. Int’l Symp. on Machine Learning for CAD (MLCAD), Sep. 2025
Patents
- Geuna Chang, Seohyun Kim, Woojin Kim, and Youngsoo Shin, “System for Verilog code automatic refinement and method for thereof,” Korea patent 10-2025-0208088, Dec. 2025, submitted.