Seunggyu Lee (이승규)
Ph.D. candidate, School of EE, KAIST
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location291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
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OfficeSchool of Electrical Engineering (E3-2), 5219
Education
- KAIST, School of Electrical Engineering Ph.D. (M.S. integrated) (Mar. 2022 – Present)
- KAIST, School of Electrical Engineering M.S. (Mar. 2021 – Feb. 2022)
- Hanyang University, School of Electronic Engineering B.S. (Mar. 2015- Feb. 2021)
- Dongin High School (Mar. 2011 – Feb. 2014)
Honors
Research Interests
- Machine learning for EDA
- Design methodology for custom circuits
- Logic synthesis for processing-in-memory (PIM)
Publications
Journal Papers
- Seunggyu Lee, Shilong Zhang, Daijoon Hyun, and Youngsoo Shin, “Accurate Timing Modeling of Custom Library Cells with Strong Non-Monotonic Behaviors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, submitted.
Conference Papers
- Umar Afzaal, Seunggyu Lee, and Youngsoo Shin, “An island style multi-objective evolutionary framework for synthesis of memristor-aided logic,” Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Jan. 2025.
- Seunggyu Lee, Wonjae Lee, and Youngsoo Shin, “Integrated netlist synthesis and in-memory mapping for memristor-aided logic,” Proc. Great Lakes Symp. on VLSI (GLSVLSI), Jun. 2024.
- Seunggyu Lee, Daijoon Hyun, Younggwang Jung, Gangmin Cho, and Youngsoo Shin, “Fast IR-drop prediction of analog circuits using recurrent synchronized GCN and Y-Net model,” Proc. Design, Automation & Test in Europe (DATE), Mar. 2024.
Patents
- Seunggyu Lee, Wonjae Lee, and Youngsoo Shin, “Method and device of in-memory mapping for memristor-aided logic,” Korea patent 10-2025-0068709, May 2025, submitted.
- Seunggyu Lee, Younggwang Jung, Daijoon Hyun, and Youngsoo Shin, “Method for predicting voltage drop in analog circuit using machine learning model and apparatus thereof,” Korea patent 10-2024-0142951, Oct. 2024.