Clock Tree Estimation

    Clock network power digital chips 40% to reach about total consumption of electricity large part accounts . However, in the actual design stage, accurate prediction is possible at a very late stage, after the clock tree synthesis (CTS) . Today's portable electronic devices have power in terms of consuming a lot of the constraints under it because the design early in the stage power analysis precisely that it is important .

In order to overcome this , the laboratory conducted a study to predict the clock network power with high accuracy at the initial stage of design and at the same time propose a clock tree synthesis input parameter for low power .

Figure 1. Clock tree estimation flow

Figure 1 is ANN (Artificial neural network) to configure the pre-layout netlist in step clock network power prediction and this through trained the ANN for using the low-power for clock tree synthesis input parameters , offering the flow shown there .  

    The research over the average 4.2% as an error clock power estimate can be had low power to optimize the parameters by suggests 16.2% Clark network power decrease can be had .


ECO Power Optimization

    Design In the second half of the engineering change order (ECO) process through design to modify more good optimized results obtained may have . As of ECO leakage optimization in step , some cell the more high threshold voltage, or no longer gate length of having cell to swap the leakage power consumption reduction can have . But this process is timing , such as constraint to It takes a long time because it has to be taken into account repeatedly . This study machine learning techniques using this fast time in effectively performing a method to study there . In particular , Graph convolutional network (GCN) the leverage gate of the feature as well as a circuit in the context of reflection by each gate of the swap results to predict it .


Figure 2. ECO leakage optimization

IR drop analysis

IR drop이란 power grid 구성하고 있는 metal wire들에서 standard cell VDD pin까지 도달하는데 발생하는 전압 강하를 의미한다. IR drop 발생하여 standard cell 공급되는 전압의 크기가 낮아지게 되면, standard cell 성능을 감소시켜서 setup violation 같은 timing violation 초래할 있다. IR drop 크게 static IR drop dynamic IR drop으로 분류되는데, static IR drop 회로에서 발생하는 평균 IR drop 의미하고 dynamic IR drop 주어진 시나리오에서 발생하는 standard cell 최대 IR drop 의미한다. 기존의 IR drop 분석하는 툴은 선형 방정식 시스템을 풀어서 IR drop 계산하지만, dynamic IR drop 경우 회로가 커질수록 시간이 많이 소요되게 되는 문제가 발생한다. 이에 연구에서는 머신 러닝 기법을 이용하여, static / dynamic IR drop 빠르게 예측하는 학습 모델을 연구하고자 한다

 
 



그림 3.  Conventional IR drop analysis                                                                                   그림 4. Machine learning-based IR drop analysis