Airgap the metal between the dielectric (inter-metal dielectric (IMD) ) in the formed intended empty a space . This IMD of the dielectric constant of 2.4 (porous SiCOH) at 2.0 or the less than (airgap with SiCOH) reduced number because , coupling capacitance reduction raises . Therefore Airgap the through wire capacitance to reduce the number of and , this circuit timing to optimize use can have . But Airgap formation 10 gaji or more additional step the process to require that the cost is high . Therefore, a limited number of metal layer to be applied may have .  This laboratory has such limited in terms Airgap the circuit timing optimization ( example : clock tree, setup constraint) to use for how the design rule for considering airgap insertion to automate the method and research there .

Directed Self-Assembly Lithography

  Directed Self-Assembly Lithography (DSAL) is gaining attention as a method for patterning small contact (via) holes in micro processes below 10 nm. In DSAL, close contact holes are grouped into contact clusters as shown in Figure (a) and patterned at once. Through a general photolithography method, a large hole (Fig. (b)) called a guide pattern is formed, and after filling it with a block copolymer (BCP), heat is applied to form two small holes by aligning the two types of polymers themselves (Fig. (c)). After that, only polymer B is removed to obtain a small contact hole (Figure (d)). In this process, if the cluster is large or complex, there may be cases where the correct contact hole cannot be obtained. In our laboratory, we are researching how to identify clusters that make DSA defects, and use this information to prevent DSA defects from occurring in various circuit design processes (placement, redundant via insertion, etc.).

Self-Aligned Double Patterning

  As devices become smaller, there are limitations in patterning using Lithography method using existing ArF, and development of Advanced Lithography such as EUV or EBL is not enough. -Patterning method is being actively applied as an alternative in sub-10nm or finer processes. Compared to LELE, which uses two masks, SADP composed of three masks has many process processes, but it is excellent in terms of layer alignment and patterning resolution, which are important for process maturity. SADP Process is mainly applied to Back-End-of-Line (BEOL). For Mandrel Pattern composed of Line Array, Cut Mask for Isolation of Lines is applied, and Block Mask for Wide Pattern formation is applied. Metal Routing improvement using SADP process, optimization of complex cut mask, and redundant via insertion are recently published in conferences and journals. 


Network clock in a digital circuit (network clock) is a clock signal from the external circuit in the memory element ( for example : latch or flip-flop) and serves to pass on . Clark network is one possible implementation of a number of ways , the most common method inverter (inverter) and the wiring (wire) tree, (tree) to form a structure . The inverter acts as an amplifier to prevent the clock signal from propagating and disappearing in the middle. As shown in [ Figure 1] , one inverter transmits the clock signal to multiple inverters again .

The general goal of the clock network design is that all memory elements receive the clock signal at the same time as possible . But not the inverter due to space restrictions will always be placed in the ideal position , which causes the time it takes to pass the clock signal to the next stage each time the inverters become different . ([ Figure 1] In this, as expressed by the horizontal axis position of the inverter and the storage element ), the difference between the time of receiving a result passes the clock signal by the storage element as there is the inevitable , this clock skew (clock skew) is called . Clock skew is one of the main factors affecting circuit performance . This is not always the case, but in general, the larger the clock skew, the lower the speed or the larger the area . Therefore, designers have used a variety of methods to reduce clock skew .

One way to reduce clock skew is to insert a crosslink . This means connecting outputs of different inverters as shown in [ Figure 1] . To illustrate by example , A and B are but a clock transmission time independently, each for being a clock signal is generated by the other inverter , C and D are two inverter is charged to a common potential node ( or discharging ) one because Only the clock signal of is generated . As a result, the memory elements connected to C and D receive clock signals at ( approximately ) the same time, so the clock skew disappears .

크로스링크는 비교적 간단한 회로 수정을 통해 클락 스큐를 제어할 수 있다는 장점이 있다. 하지만 크로스링크로 연결한 두 인버터의 출력단이 생성한 클락 신호는 정확히 언제 생성되는지, 어느 인버터들을 연결해야 최소한의 배선으로 최대의 클락 스큐 감소를 유도할 수 있는지 등의 문제를 풀어야 한다. 이에 본 연구실에서는 회로 해석과 최적화 기법을 통해 제기된 문제들을 풀기 위해 노력하고 있다

그림 1. Crosslink

    Phase Change Memory (PCM) DRAMNAND Flash 와 비교하였을 때 더 나은 scalability와 적은 대기전력 소모, 그리고 더 큰 저장 공간 밀도로 가장 각광받는 emerging 메모리 기술 중 하나이다. 하지만 이 PCM이  현재 메모리 시스템에 적용되기에는 몇몇의 해결되지 못한 문제들이 아직 남아있다. PCM에서 각 celldata를 저장하는 GST 물질에 아주 높은 전류를 통하게 하여 열을 발생 시켜 쓰기 때문에, DRAM에 미치지 못하는 내구성(endurance)과 쓰기 속도(latency)와 쓰기 에너지 소모가 그 한계점이다. 본 연구실에서는 이러한 PCM의 한계를 개선하기 위해 data encoding 방법과 cell program 방법을 포함한 시스템 아키텍처 수준에서의 개선 방법을 연구하고 있다.