Today, portable electronic devices (smartphones, tablets, etc.) are required to be as power-efficient as desktop PCs while consuming less power. Power consumption has become one of the major constraints in the design of semiconductor chips for portable electronic devices, and low-power design has long been an integral part of semiconductor chip design. For an efficient low-power design, it is imperative that the power analysis be accompanied by the need to know which block is consuming the power when doing some operation. But here we are faced with the dilemma of low power design. As shown in Figure 1, the amount of power that can be saved through the low-power design is very large in the early stages of the design flow  .On the other hand, in the latter stage, high accuracy power analysis is possible, but the amount of power consumption that can be saved is too small.
  To overcome this problem, we are developing a new power analysis tool that can obtain a very accurate power waveform at the initial stage of design. Figure 2 shows the power analysis using the tool. This tool provides netlist and power information at the gate level at the later stage of the design,  signal transition information (FSDB / VCD) on the netlist. Based on this information, we generate a usable power model from the higher level functional simulator. Now, when the simulator is running in conjunction with this power model, accurate power waveforms can be obtained in real time at higher levels. Currently, the tool can predict power at 100 times faster than power analysis tools at the gate level, and the average power error is within 10%.