Conference
  1. Sunwha Koh, Yonghwi Kwon, and Youngsoo Shin, "Pre-layout clock tree estimation and optimization using artificial neural network," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), Aug. 2020, accepted. 
  2. Wonjae Lee, Yonghwi Kwon, and Youngsoo Shin, "Fast ECO leakage optimization using graph convolutional network," Proc. Great Lakes Symp. on VLSI (GLSVLSI), Sep. 2020, accepted.
  3. Yonghwi Kwon, Jinho Yang, Sungho Kim, Cheolkyun Kim, and Youngsoo Shin, "SRAF printing prediction using artificial neural network," Proc. SPIE Advanced Lithography, Feb. 2020.
  4. Younggwang Jung, Daijoon Hyun, and Youngsoo Shin, "Integrated airgap insertion and layer reassignment for circuit timing optimization," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 32-37, Jan. 2020. (Nominated for Best Paper Award)
  5. Cheongwon Lee, Youngsoo Song, and Youngsoo Shin, "Endurance enhancement of multi-level cell phase change memory," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), Nov. 2019.
  6. Yonghwi Kwon, Inhak Han, and Youngsoo Shin, "Clock gating synthesis of netlist with cyclic logic paths," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), Nov. 2019.
  7. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, "Standard cell layout design and placement optimization for TFET-based circuits," Proc. Int'l Symp. on Circuits and Systems (ISCAS),  May 2019.
  8. Daijoon Hyun, Yuepeng Fan, and Youngsoo Shin, "Accurate wirelength prediction for placement-aware synthesis through machine learning," Proc. Design, Automation & Test in Europe (DATE), pp. 324-327, Mar. 2019.
  9. Yonghwi Kwon, Youngsoo Song, and Youngsoo Shin, "Optical proximity correction using bidirectional recurrent neural network (BRNN)," Proc. SPIE Advanced Lithography, Feb. 2019.
  10. Joonhyuk Cho, Gangmin Cho, and Youngsoo Shin, "Optimization of machine learning guided optical proximity correction," Proc. Int'l Midwest Symp. on Circuits and Systems (MWSCAS), pp. 921-924, Aug. 2018. PDFpaper
  11. Kiwon Yoon, Daijoon Hyun, and Youngsoo Shin, "Fast timing analysis of non-tree clock network with shorted wires," Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 279-284, May 2018.PDFpaper
  12. Yonghwi Kwon, Jinwook Jung, Inhak Han, and Youngsoo Shin, "Transient clock power estimation of pre-CTS netlist," Proc. Int'l Symp. on Circuits and Systems (ISCAS), May 2018.PDFpaper
  13. Daijoon Hyun, Jaewoo Seo, and Youngsoo Shin, "Library optimization for near threshold voltage design,"  Proc. Int'l Symp. on Circuits and Systems (ISCAS), May 2018.PDFpaper
  14. Jingon Lee, Jinwook Jung, and Youngsoo Shin, "Fast timing analysis of transistor-level full custom digital circuits," Proc. Int'l Symp. on Circuits and Systems (ISCAS), May 2018.PDFpaper
  15. Jaewoo Seo, Jinwook Jung, and Youngsoo Shin, "A compact multi-bit flip-flop with smaller height implementation and metal-less clock routing," Proc. SPIE Advanced Lithography, pp. 1-9 (105880A), Feb. 2018.PDFpaper
  16. Youngsoo Song, Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, "Timing optimization in SADP process through wire widening and double via insertion," Proc. SPIE Advanced Lithography, pp. 1-7, Feb. 2018.PDFpaper
  17. Daijoon Hyun and Youngsoo Shin, "Automatic insertion of airgap with design rule constraints," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 381-386, Jan. 2018.PDFpaper
  18. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, "Redundant via insertion in SADP process with cut merging and optimization," Proc. Int'l Conf. on Very Large Scale Integration (VLSI-SoC), pp. 1-6, Oct. 2017. (Invited Paper)PDFpaper
  19. Jaewoo Seo, Jinwook Jung, Sangmin Kim, and Youngsoo Shin, "Pin accessibility-driven cell layout redesign and placement optimization," Proc. Design Automation Conf. (DAC), pp. 54:1-54:6, June 2017.PDFpaper
  20. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, "Redundant via insertion with cut optimization for self-aligned double patterning," Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 137-142, May 2017.PDFpaper
  21. Youngsoo Song, Sangmin Kim, and Youngsoo Shin, "Timing-aware wire width optimization for SADP process," Proc. Design, Automation & Test in Europe (DATE), pp. 1639-1642, Mar. 2017. PDFpaper
  22. Wachirawit Ponghiran, Seongbo Shim, and Youngsoo Shin, "Cut mask optimization for multi-patterning directed self-assembly lithography," Proc. Design, Automation & Test in Europe (DATE), pp. 1498-1503, Mar. 2017. PDFpaper
  23. Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin, "Clock tree optimization through selective airgap insertion," Proc. Int'l Symp. on Quality Electronic Design (ISQED), pp. 203-208, Mar. 2017. PDFpaper
  24. Jaewoo Seo and Youngsoo Shin, "Routability enhancement through unidirectional standard cells with floating metal-2," Proc. SPIE Advanced Lithography, pp. 1-8 (101480K), Feb. 2017. PDFpaper
  25. Daijoon Hyun and Youngsoo Shin, "Selection of airgap layers for circuit timing optimization," Proc. SPIE Advanced Lithography, pp. 1-8 (101480O), Feb. 2017. PDFpaper
  26. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, "Redundant via insertion in self-aligned double patterning," Proc. SPIE Advanced Lithography, pp. 1-8 (1014806), Feb. 2017. PDFpaper
  27. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, "Machine learning-based resist 3D model," Proc. SPIE Advanced Lithography, pp. 1-10 (101471D), Feb. 2017. PDFpaper
  28. Suhyeong Choi, Jae Uk Lee, Victor Blanco, Ryoung-Han Kim, and Youngsoo Shin, "2D self-aligned via patterning strategy with EUV single exposure in 3nm technology," Proc. SPIE Advanced Lithography, pp. 1-8 (1014321), Feb. 2017. PDFpaper
  29. Suhyeong Choi, Jae Uk Lee, Victor Blanco, Peter Debacker, Praveen Raghavan, Ryoung-Han Kim, and Youngsoo Shin, "Large marginal 2D self-aligned via patterning for sub-5nm technology," Proc. SPIE Advanced Lithography, pp. 1-10 (101480J), Feb. 2017. PDFpaper
  30. Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, "OWARU: free space-aware timing-driven incremental placement," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 8:1–8:8, Nov. 2016. PDFpaper
  31. Sangmin Kim, Ik Joon Chang, and Youngsoo Shin, "Synthesis of dual-mode circuits through optimizing transition time constraints," Proc. Int'l Conf. on Consumer Electronics, pp. 97-99, Oct. 2016.
  32. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, "Machine learning (ML)-based lithography optimizations," Proc. Asia Pacific Conf. on Circuits and Systems (APCCAS), pp. 530-533, Oct. 2016. (Invited Paper)PDFpaper
  33. Kiwon Yoon, Suhyeong Choi, and Youngsoo Shin, "Area efficient neuromorphic circuit based on stochastic computation," Proc. Int'l SoC Design Conf. (ISOCC), pp. 73-74, Oct. 2016.PDFpaper
  34. Jinwook Jung and Youngsoo Shin, "Localized DNA circuit design with majority gates," Proc. BioMedical Circuits and Systems Conf., pp. 172–175, Oct. 2016.PDFpaper
  35. Inhak Han, Jonggyu Kim, Joonhwan Yi, and Youngsoo Shin, "Register grouping for synthesis of clock gating logic," Proc. Int'l Conf. on IC Design & Technology (ICICDT), June 2016.PDFpaper
  36. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Placement optimization for MP-DSAL compliant layout," Proc. Int'l Conf. on IC Design & Technology (ICICDT), June 2016. (Invited Paper)PDFpaper
  37. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Redundant via insertion for multiple-patterning directed-self-assembly lithography," Proc. Design Automation Conf. (DAC), pp. 41:1-41:6 June 2016.PDFpaper
  1. Kiwon Yoon, Seongbo Shim, and Youngsoo Shin, "Crosslink insertion for minimizing OCV clock skew," Proc. Int'l Symp. on Circuits and Systems (ISCAS), pp. 2587-2590, May 2016.PDFpaper
  2. Woohyun Chung, Seongbo Shim, and Youngsoo Shin, "Redundant via insertion in directed self-assembly lithography," Proc. Design, Automation & Test in Europe (DATE), pp. 55-60, Mar. 2016.PDFpaper
  3. Daijoon Hyun and Youngsoo Shin, "Modeling interconnect corners under double patterning misalignment," Proc. SPIE Advanced Lithography, pp. 97810F-97810F-7, Feb. 2016. PDFpaper
  4. Youngsoo Song, Jeemyung Lee, Seongmin Lee and Youngsoo Shin, "Integrated routing and fill for self-aligned double patterning (SADP) using grid-based design," Proc. SPIE Advanced Lithography, pp. 978105-978105-8, Feb. 2016. PDFpaper
  5. Seongbo Shim and Youngsoo Shin, "Etch proximity correction through machine-learning-driven etch bias model," Proc. SPIE Advanced Lithography, pp. 97820O-97820O-10, Feb. 2016. PDFpaper
  6. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Machine learning (ML)-guided OPC using basis functions of polar Fourier transform," Proc. SPIE Advanced Lithography, pp. 97800H-97800H-8, Feb. 2016. PDFpaper
  7. Seongbo Shim and Youngsoo Shin, "Mask optimization for directed self-assembly lithography: inverse DSA and inverse lithography," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp.83-88, Jan. 2016. PDFpaper
  8. Inhak Han, Daijoon Hyun, and Youngsoo Shin, "Buffer insertion to remove hold violations at multiple process corners,"  Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 232-237, Jan. 2016. PDFpaper
  9. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Defect probability of directed self-assembly lithography: fast identification and post-placement optimization," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 404-409, Nov. 2015. PDFpaper
  10. Daijoon Hyun and Youngsoo Shin, "Calibration of interconnect corners using on-chip ring oscillators," Proc. Int'l SoC Design Conf. (ISOCC), pp. 141-142, Nov. 2015. (Best Paper Award) PDFpaper
  11. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Electrothermal analysis with generalized boundary conditions," Proc. Int'l SoC Design Conf. (ISOCC), pp. 39-40, Nov. 2015. PDFpaper
  12. Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, "Physical synthesis of DNA circuits with spatially localized gates," Proc. Int'l Conf. on Computer Design (ICCD), pp. 280-286, Oct. 2015. PDFpaper
  13. Seongbo Shim and Youngsoo Shin, "Physical design and mask optimization for directed self-assembly lithography (DSAL)," Proc. Int'l Conf. on Very Large Scale Integration (VLSI-SoC), pp. 80-85, Oct. 2015. PDFpaper
  14. Woohyun Chung, Seongbo Shim, and Youngsoo Shin, "Identifying redundant inter-cell margins and its application to reducing routing congestion," Proc. Design, Automation & Test in Europe (DATE), pp. 1659-1664, Mar. 2015. PDFpaper
  15. Seongbo Shim, Sibo Cai, Jaewon Yang, Seunghune Yang, Byungil Choi, and Youngsoo Shin, "Verification of direct self-assembly (DSA) guide patterns through machine learning," Proc. SPIE Advanced Lithography, pp. 94231E-94231E-8, Mar. 2015. PDFpaper
  16. Jinwook Jung, Dongsoo Lee, and Youngsoo Shin, "Design and optimization of multiple-mesh clock network," Proc. Int'l Conf. on Very Large Scale Integration (VLSI-SoC), pp. 171-176, Oct. 2014. PDFpaper
  17. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Synthesis of lithography test patterns through topology-oriented pattern extraction and classification," Proc. SPIE Advanced Lithography, pp. 1-10 (905305), Feb. 2014. PDFpaper
  18. Seongbo Shim, Yoojong Lee, and Youngsoo Shin, "Lithographic defect aware placement using compact standard cells without inter-cell margin," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 47-52, Jan. 2014. PDFpaper
  19. Insup Shin, Jae-Joon Kim, and Youngsoo Shin, "Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 179-184, Jan. 2014. PDFpaper
  20. Yongsoo Ahn, Donkyu Baek, Dongsoo Lee, and Youngsoo Shin, "Pulsed-Vdd: synchronous circuit design without clock network," Proc. Int'l SoC Design Conf. (ISOCC), pp. 192-193, Nov. 2013.PDFpaper
  21. Seongbo Shim, Minyoung Mo, Sangmin Kim, and Youngsoo Shin, "Analysis and minimization of short-circuit current in mesh clock network," Proc. Int'l Conf. on Computer Design (ICCD), pp. 459-462, Oct. 2013. PDFpaper
  22. Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, and Youngsoo Shin, "A pipeline architecture with 1-cycle timing error correction for low voltage operations," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), pp. 199-204, Sep. 2013. PDFpaper
  23. Inhak Han and Youngsoo Shin, "Folded circuit synthesis: logic simplification using dual edge-triggered flip-flops," Proc. Int'l Conf. on IC Design & Technology (ICICDT), pp. 17-20, May 2013. PDFpaper
  24. Sangmin Kim, Duckhwan Kim, and Youngsoo Shin, "Pulsed-latch ASIC synthesis in industrial design flow," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 356-361, Jan. 2013. PDFpaper
  25. Insup Shin, Donkyu Baek, and Youngsoo Shin, "Introducing irregularity to routing architecture of structured ASIC for better routability," Proc. Int'l Conf. on Field-Programmable Technology (FPT), pp. 224-228, Dec. 2012. PDFpaper
  26. Donkyu Baek, Insup Shin, and Youngsoo Shin, "Gate delay modeling for static timing analysis of body-biased circuits," Proc. Int'l Conf. on IC Design & Technology (ICICDT), May 2012. PDFpaper
  27. Inhak Han and Youngsoo Shin, "Synthesis of clock gating logic through factored form matching," Proc. Int'l Conf. on IC Design & Technology (ICICDT), May 2012. PDFpaper
  28. Jaeha Kung and Youngsoo Shin, "Compact thermal models: assessment and pitfalls," Proc. Int'l SoC Design Conf. (ISOCC), pp. 337-340, Nov. 2011. (Invited Paper)PDFpaper
  29. Seungwhun Paik, Gi-Joon Nam, and Youngsoo Shin, "Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 640-646, Nov. 2011. PDFpaper
  30. Seungwhun Paik, Jaeha Kung, and Youngsoo Shin, "Exploring the opportunity of optimizing sequencing elements in ASIC designs," Proc. Int'l Midwest Symp. on Circuits and Systems (MWSCAS), pp. 394-397, Aug. 2011. (Invited Paper)PDFpaper
  31. Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, and Youngsoo Shin, "Thermal signature: a simple yet accurate thermal index for floorplan optimization," Proc. Design Automation Conf. (DAC), pp. 108-113, June 2011. PDFpaper
  32. Donkyu Baek, Insup Shin, Seungwhun Paik, and Youngsoo Shin, "Selectively patterned masks: structured ASIC with asymptotically ASIC performance," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 376-381, Jan. 2011. PDFpaper
  33. Sangmin Kim, Inhak Han, Seungwhun Paik, and Youngsoo Shin, "Pulser gating: a clock gating of pulsed-latch circuits," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 190-195, Jan. 2011. PDFpaper
  34. Donkyu Baek, Insup Shin, Seungwhun Paik, and Youngsoo Shin, "Selectively patterned masks: beyond structured ASIC," Proc. Int'l SoC Design Conf. (ISOCC), pp. 154-157, Nov. 2010. (Invited Paper)PDFpaper
  35. Seungwhun Paik and Youngsoo Shin, "Pulsed-latch circuits to push the envelope of ASIC design," Proc. Int'l SoC Design Conf. (ISOCC), pp. 150-153, Nov. 2010. (Invited Paper)PDFpaper
  36. Seungwhun Paik, Sangmin Kim, and Youngsoo Shin, "Wakeup synthesis and its buffered tree construction for power gating circuit designs," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), pp. 413-418, Aug. 2010. PDFpaper
  37. Jun Seomun, Insup Shin, and Youngsoo Shin, "Synthesis and implementation of active mode power gating circuits," Proc. Design Automation Conf. (DAC), pp. 487-492, June 2010. PDFpaper
  38. Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, and Yao-Wen Chang, "Pulsed-latch-aware placement for timing-integrity optimization," Proc. Design Automation Conf. (DAC), pp. 280-285, June 2010. PDFpaper
  39. Inhak Han, Lee-eun Yu, and Youngsoo Shin, "Fast Monte Carlo method via reduced sample number and node filtering," Proc. Int'l Conf. on IC Design & Technology (ICICDT), pp. 126-129, June 2010. PDFpaper
  40. Seungwhun Paik, Lee-eun Yu, and Youngsoo Shin, "Statistical time borrowing for pulsed-latch circuit designs," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 675-680, Jan. 2010. PDFpaper
  41. Jun Seomun, Seungwhun Paik, and Youngsoo Shin, "Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 581-586, Jan. 2010. PDFpaper
  42. Jun Seomun and Youngsoo Shin, "Self-retention of data in power-gated circuits," Proc. Int'l SoC Design Conf. (ISOCC), pp. 212-215, Nov. 2009. (Invited Paper)PDFpaper
  43. Seonggwan Lee, Seungwhun Paik, and Youngsoo Shin, "Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 375-380, Nov. 2009.PDFpaper
  44. Nam Sung Kim, Jun Seomun, Abhishek Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, and Youngsoo Shin, "Frequency and yield optimization using power gates in power-constrained designs," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), pp. 121-126, Aug. 2009.PDFpaper
  45. Insup Shin, Seungwhun Paik, and Youngsoo Shin, "Register allocation for high-level synthesis using dual supply voltages," Proc. Design Automation Conf. (DAC), pp. 937-942, July 2009.PDFpaper
  46. Lee-eun Yu, Changsik Shin, Jing-Jia Liou, and Youngsoo Shin, "Timing yield estimation with clock network correlations by propagating discrete probability distributions," Proc. Int'l Conf. on IC Design & Technology (ICICDT), pp. 63-66, May 2009.PDFpaper
  47. Chungki Oh, Sangmin Kim, and Youngsoo Shin, "Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating," Proc. Int'l Conf. on IC Design & Technology (ICICDT), pp. 59-62, May 2009.PDFpaper
  48. Seungwhun Paik, Insup Shin, and Youngsoo Shin, "HLS-l: high-level synthesis of high performance latch-based circuits," Proc. Design, Automation & Test in Europe (DATE), pp. 1112-1117, Apr. 2009.PDFpaper
  49. Hyein Lee, Seungwhun Paik, and Youngsoo Shin, "Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 224-229, Nov. 2008.PDFpaper
  50. Eunjoo Choi, Changsik Shin, Taewhan Kim, and Youngsoo Shin, "Power-gating-aware high-level synthesis," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), pp. 39-44, Aug. 2008.PDFpaper
  51. Seungwhun Paik and Youngsoo Shin, "Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements," Proc. Design Automation Conf. (DAC), pp. 600-605, June 2008.PDFpaper
  52. Eunjoo Choi and Youngsoo Shin, "3-D thermal simulation with dynamic power profiles," Proc. IEEE Int'l Symp. on Circuits and Systems (ISCAS), pp. 2765-2769, May 2008.PDFpaper
  53. Jinseob Jeong, Seungwhun Paik, and Youngsoo Shin, "Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 629-634, Jan. 2008.PDFpaper
  54. Sewan Heo and Youngsoo Shin, "Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping," Proc. Int'l SoC Design Conf. (ISOCC), Oct. 2007.PDFpaper
  55. Jae-hyun Kim and Youngsoo Shin, "Minimizing leakage power in sequential circuits by using mixed Vt flip-flops," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 797-802, Nov. 2007.PDFpaper
  56. Jun Seomun, Jae-hyun Kim, and Youngsoo Shin, "Skewed flip-flop transformation for minimizing leakage in sequential circuits," Proc. Design Automation Conf. (DAC), pp. 103-106, June 2007.PDFpaper
  57. Youngsoo Shin and Hyung-Ock Kim, "Cell-based semicustom design of zigzag power gating circuits," Proc. Int'l Symp. on Quality Electronic Design (ISQED), pp. 527-532, Mar. 2007.PDFpaper
  58. Byunghee Choi and Youngsoo Shin, "Lookup table-based adaptive body biasing of multiple macros," Proc. Int'l Symp. on Quality Electronic Design (ISQED), pp. 533-538, Mar. 2007. (Nominated for Best Paper Award)PDFpaper
  59. Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, and Jung Yun Choi, "Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 654-659, Jan. 2007.PDFpaper
  60. Byunghee Choi and Youngsoo Shin, "Fine-grain control of multiple functional blocks with lookup table-based adaptive body biasing," Proc. Int'l SoC Design Conf. (ISOCC), pp. 357-360, Oct. 2006 (Best Paper Award)PDFpaper
  61. Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, and Iksoo Eo, "Physical design methodology of power gating circuits for standard-cell-based design," Proc. Design Automation Conf. (DAC), pp. 109-112, July 2006.PDFpaper
  62. Sewan Heo, Hyung-Ock Kim, and Youngsoo Shin, "Power gating and supply control for low standby leakage power of VLSI circuits," Proc. Symp. on Low-Power and High-Speed Chips (COOL Chips), pp. 305-307, Apr. 2006.PDFpaper
  63. Hyung-Ock Kim and Youngsoo Shin, "Analysis and optimization of gate leakage current of power gating circuits," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 565-569, Jan. 2006.PDFpaper
  64. Hyung-Ock Kim and Youngsoo Shin, "Power-aware slack distribution for hierarchical VLSI design," Proc. IEEE Int'l Symp. on Circuits and Systems (ISCAS), pp. 4150-4153, May 2005. PDFpaper
  65. Youngsoo Shin and Hyung-Ock Kim, "Analysis of power consumption in VLSI global interconnects," Proc. IEEE Int'l Symp. on Circuits and Systems (ISCAS), pp. 4713-4716, May 2005. PDFpaper
  66. Subhrajit Bhattacharya, John Darringer, Daniel Ostapko, and Youngsoo Shin, "A mask reuse methodology for reducing System-on-a-Chip cost," Proc. Int'l Symp. on Quality Electronic Design (ISQED), pp. 482-487, Mar. 2005. (Best Paper Award)PDFpaper
  67. Nagu Dhanwada, Reinaldo A. Bergamaschi, William Dungan, Indira I. Nair, William E. Dougherty, Youngsoo Shin, Subhrajit Bhattacharya, Ing-Chao Lin, John Darringer, and Sarala Paliwal, "Simultaneous exploration of power, physical design, and architectural performance dimensions of SoC design space using SEAS," Proc. IP Based SoC Design Forum & Exhibition (IP-SoC), Dec. 2004. PDFarticle
  68. Jingcao Hu, Youngsoo Shin, Nagu Dhanwada, and Radu Marculescu, "Architecting voltage islands in core-based System-on-a-Chip designs," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), pp. 180-185, Aug. 2004. PDFpaper
  69. Dan Knebel, Stephen Kosonocky, Subhrajit Bhattacharya, Ruchir Puri, and Youngsoo Shin, “Leakage control through fine-grained power gating: methodology and implementation,” Proc. IBM Austin Conf. on Energy-Efficient Design (ACEED), Mar. 2004.
  70. Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira I. Nair, John Darringer, and Sarala Paliwal, "SEAS: a system for early analysis of SoCs," Proc. Int'l Conf. on Hardware/Software Codesign and System Synthesis, pp. 150-155, Oct. 2003. PDFpaper
  71. Indira I. Nair, Youngsoo Shin, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, John Darringer, and Stephen Kosonocky, “Modeling and analysis of power for System-on-a-Chip design,” Proc. IBM Austin Conf. on Energy-Efficient Design (ACEED), Mar. 2003.
  72. S. Kim, Youngsoo Shin, Stephen Kosonocky, and W. Hwang, "Long-term power minimization of dual-Vt CMOS circuits," Proc. Int'l ASIC/SOC Conf., pp. 323-327, Sep. 2002.PDFpaper
  73. Youngsoo Shin and Takayasu Sakurai, "Estimation of power distribution in VLSI interconnects," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), pp. 370-375, Aug. 2001. PDFpaper
  74. Youngsoo Shin and Takayasu Sakurai, "Coupling-driven bus design for low-power application-specific systems," Proc. Design Automation Conf. (DAC), pp. 750-753, June 2001. PDFpaper
  75. Hiroshi Kawaguchi, Youngsoo Shin, and Takayasu Sakurai, "Experimental evaluation of cooperative voltage scaling (CVS): a case study," Proc. IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp. 17-23, May 2001. PDFpaper
  76. Youngsoo Shin, Hiroshi Kawaguchi, and Takayasu Sakurai, "Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems," Proc. Custom Integrated Circuits Conf. (CICC), pp. 553-556, May 2001. PDFpaper
  77. Youngsoo Shin, Kiyoung Choi, and Takayasu Sakurai, "Power optimization of real-time embedded systems on variable speed processors," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 365-368, Nov. 2000. PDFpaper
  78. Youngsoo Shin, Daehong Kim, and Kiyoung Choi, "Schedulability-driven performance analysis of multiple mode embedded real-time systems," Proc. Design Automation Conf. (DAC), pp. 495-500, June 2000. PDFpaper
  79. Youngsoo Shin and Kiyoung Choi, "Narrow bus encoding for low power systems," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 217-220, Jan. 2000. PDFpaper
  80. Youngsoo Shin and Kiyoung Choi, "Power conscious fixed priority scheduling for hard real-time systems," Proc. Design Automation Conf. (DAC), pp. 134-139, June 1999. PDFpaper
  81. Youngsoo Shin and Kiyoung Choi, "Rate assignment for embedded reactive real-time systems," Proc. Euromicro Workshop on Digital Systems Design, pp. 237-242, Aug. 1998.
  82. Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, "Partial bus-invert coding for power optimization of system level bus," Proc. Int'l Symp. on Low Power Electronics and Design (ISLPED), pp. 127-129, Aug. 1998. PDFpaper
  83. Youngsoo Shin and Kiyoung Choi, "Enhancing schedulability of hard real-time systems through codesign," Proc. IEEE Int'l Symp. on Circuits and Systems (ISCAS), pp. 1576-1579, June 1997.
  84. Youngsoo Shin and Kiyoung Choi, "Enforcing schedulability of multi-task systems by hardware-software codesign," Proc. 5th Int'l Workshop on Hardware/Software Co-Design (Codes/CASHE), pp. 3-7, Mar. 1997. PDFpaper
  85. Youngsoo Shin and Kiyoung Choi, "Software synthesis through task decomposition by dependency analysis," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 98-102, Nov. 1996. PDFpaper
  86. Kyuseok Kim, Yongjoo Kim, Youngsoo Shin, and Kiyoung Choi, "An integrated hardware-software cosimulation environment with automated interface generation," Proc. 7th IEEE Int'l Workshop on Rapid Systems Prototyping, pp. 66-71, June 1996.
  87. Youngsoo Shin and Kiyoung Choi, "Thread-based software synthesis for embedded system design," Proc. European Design & Test Conf. (ED&TC), pp. 282-286, Mar. 1996.
  88. Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, and Soonhoi Ha, "An integrated hardware-software cosimulation environment for heterogeneous systems prototyping," Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), pp. 101-106, Aug. 1995.
  89. Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jaehee Won, and Kiyoung Choi, "Efficient prototyping system based on incremental design and module-by-module verification," Proc. IEEE Int'l Symp. on Circuits and Systems (ISCAS), pp. 924-927, Apr. 1995.
Note Many of the papers above have been made available for easy access. Please be aware that they are copyrighted by the organization responsible for the corresponding conference or journal.