Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, "OWARU: free space-aware timing-driven incremental placement with critical path smoothing," IEEE Transactions on CAD of Integrated Circuits and Systems, under review.
Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Neural network classifier-based OPC with imbalanced training data," IEEE Transactions on CAD of Integrated Circuits and Systems, under review.
Inhak Han and Youngsoo Shin, "Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops," IEEE Transactions on CAD of Integrated Circuits and Systems, under review.
Sangmin Kim and Youngsoo Shin, "Module grouping to reduce the area of test wrappers in SoCs," Integration, the VLSI Journal, in revision.
Seongbo Shim and Youngsoo Shin, “Fast verification of guide patterns for directed self-assembly lithography," IEEE Transactions on CAD of Integrated Circuits and Systems, accepted for publication.
Seongbo Shim and Youngsoo Shin, "Machine learning-guided etch proximity correction," IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 1, pp. 1-7, Feb. 2017. paper
Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Lithography defect probability and its application to physical design optimization,” IEEE Transactions on Very Large Scale Integration Systems, vol. 25, no. 1, pp. 271-285, Jan. 2017. paper
Byoung Kuk You, Jong Min Kim, Daniel J. Joe, Kyounghoon Yang, Youngsoo Shin, Yeon Sik Jung, and Keon Jae Lee, "Reliable memristive switching memory devices enabled by densely packed silver nanocone arrays as electric-field concentrators," ACS Nano, 10(10), pp. 9478-9488, Oct. 2016. paper
Sangmin Kim, Seokhyeong Kang, and Youngsoo Shin, “Synthesis of dual-mode circuits through library design, gate sizing, and clock tree optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 21, no.3, pp. 51, May 2016.paper
Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, and Youngsoo Shin, "Wakeup scheduling and its buffered tree synthesis for power gating circuits," Integration, the VLSI Journal, vol. 53, pp. 157-170, Mar. 2016.paper
Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, "Light interference map: a prescriptive optimization of lithography-friendly layout," IEEE Transactions on Semiconductor Manufacturing, vol. 29, pp.44-49, Feb. 2016. paper
Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, and Youngsoo Shin, “One-cycle correction of timing errors in pipelines with standard clocked elements,” IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 2, pp. 600-612, Feb. 2016. paper
Seongbo Shim, Jae Wook Lee, and Youngsoo Shin, "An analytical approach to thermal design and optimization with a temperature-dependent power model," IEEE Transactions on Circuits and Systems I, vol. 62, no. 3, pp. 816-824, Mar. 2015. paper
Insup Shin, Jae-Joon Kim, and Youngsoo Shin, "Aggressive voltage scaling through fast correction of multiple errors with seamless pipeline operation," IEEE Transactions on Circuits and Systems I, vol. 62, no. 2, pp. 468-477, Feb. 2015. paper
Seongbo Shim and Youngsoo Shin, "Topology-oriented pattern extraction and classification for synthesizing lithography test patterns," Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 14(1), no. 013503, pp. 1-12, Jan. 2015. paper
Inhak Han and Youngsoo Shin, “Simplifying clock gating logic by matching factored forms,” IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 6, pp. 1338-1349, June 2014. paper
Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, and Seungwhun Paik, “HAPL: heterogeneous array of programmable logic using selective mask patterning,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 1, pp. 146-159, Jan. 2014. paper
Donkyu Baek, Insup Shin, and Youngsoo Shin, “Accurate gate delay extraction for timing analysis of body-biased circuits,” Journal of Circuits, Systems, and Computers, vol. 22, no. 8, Sep. 2013.paper
Nam Sung Kim, Abhishek Sinkar, Jun Seomun, and Youngsoo Shin, “Maximizing frequency and yield of power-constrained designs using programmable power-gating,” IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 10, pp. 1885-1890, Oct. 2012.paper
Seungwhun Paik, Inhak Han, Sangmin Kim, and Youngsoo Shin, “Clock gating synthesis of pulsed-latch circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 7, pp. 1019-1030, July 2012.paper
Insup Shin, Seungwhun Paik, Dongwan Shin, and Youngsoo Shin, “HLS-dv: a high-level synthesis framework for dual-Vdd architectures,” IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 4, pp. 593-604, Apr. 2012.paper
Jun Seomun, Insup Shin, and Youngsoo Shin, “Synthesis of active-mode power-gating circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 31, no. 3, pp. 391-403, Mar. 2012.paper
Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, and Youngsoo Shin, “Sampling correlation sources for timing yield analysis of sequential circuits with clock networks,” Journal of Circuits, Systems, and Computers, vol. 20, no. 8, pp. 1547-1569, Dec. 2011.paper
Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, and Yao-Wen Chang, “Pulsed-latch aware placement for timing-integrity optimization,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 30, no. 12, pp. 1856-1869, Dec. 2011.paper
Youngsoo Shin and Seungwhun Paik, “Pulsed-latch circuits: a new dimension in ASIC design,” IEEE Design & Test of Computers, vol. 28, no. 6, pp. 50-57, Nov./Dec. 2011.paper
Seungwhun Paik, Seonggwan Lee, and Youngsoo Shin, “Retiming pulsed-latch circuits with regulating pulse width,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 30, no. 8, pp. 1114-1127, Aug. 2011.paper
Jun Seomun and Youngsoo Shin, “Design and optimization of power-gated circuits with autonomous data-retention,” IEEE Transactions on Very Large Scale Integration Systems, vol. 19, no. 2, pp. 227-236, Feb. 2011.paper
Byunghee Choi and Youngsoo Shin, “Lookup table-based adaptive body biasing of multiple macros for process variation compensation and low leakage,” Journal of Circuits, Systems, and Computers, vol. 19, no. 7, pp. 1449-1464, Nov. 2010.paper
Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, and Takayasu Sakurai, “Power gating: circuits, design methodologies, and best practice for standard-cell VLSI designs,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 4, article 28, pp. 28:1-28:37, Sep. 2010. (Top 10 most downloaded ACM TODAES articles published in 2010)paper
Seungwhun Paik, Insup Shin, Taewhan Kim, and Youngsoo Shin, “HLS-l: a high-level synthesis framework for latch-based architectures,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 5, pp. 657-670, May 2010paper
Hyein Lee, Seungwhun Paik, and Youngsoo Shin, “Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 29, no. 3, pp. 355-366, Mar. 2010. (Top 25 most downloaded articles for IEEE TCAD in 2010)paper
Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, and Youngsoo Shin, “Supply switching with ground collapse for low-leakage register files in 65-nm CMOS,” IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 3, pp. 505-509, Mar. 2010.paper
Jaehyun Kim, Chungki Oh, and Youngsoo Shin, “Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 1, article 4, pp. 4:1-4:22, Dec. 2009.paper
Eunjoo Choi, Changsik Shin, and Youngsoo Shin, “HLS-pg: high-level synthesis of power-gated circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 28, no. 3, pp. 451-456, Mar. 2009.paper
Youngsoo Shin, Seungwhun Paik, and Hyung-Ock Kim, “Semicustom design of zigzag power-gated circuits in standard cell elements,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 28, no. 3, pp. 327-339, Mar. 2009.paper
Jun Seomun, Jae-hyun Kim, and Youngsoo Shin, “Skewed flip-flop and mixed-Vt gates for minimizing leakage in sequential circuits,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 27, no. 11, pp. 1956-1968, Nov. 2008.paper
Sewan Heo and Youngsoo Shin, “Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping,” Journal of Semiconductor Technology and Science, vol.7, no.4, pp. 215-220, Dec. 2007.paper
Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, and Jung Yun Choi, “Supply switching with ground collapse: simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits,” IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 7, pp. 758-766, July 2007. paper
Hyung-Ock Kim and Youngsoo Shin, “Semicustom design methodology of power gated circuits for low leakage applications,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 6, pp. 512-516, June 2007.paper
Youngsoo Shin and Junghyup Lee, “Power analysis of VLSI interconnect with RLC tree models and model reduction,” Journal of Circuits, Systems, and Computers, vol. 15, no. 3, pp.399-408, June 2006.paper
Hiroshi Kawaguchi, Youngsoo Shin, and Takayasu Sakurai, “uITRON-LP: power conscious real-time OS based on cooperative voltage scaling for multimedia applications,” IEEE Transactions on Multimedia, vol. 7, no. 1, pp. 177-185, Feb. 2005. (Corresponding project received LSI IP Design Award in 2002)paper
John Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira I. Nair, Patricia Sagmeister, and Youngsoo Shin, “Early analysis tools for System-on-a-Chip design,” IBM Journal of Research and Development, vol. 46, no. 6, pp. 691-707, Nov. 2002.paper
Youngsoo Shin and Takayasu Sakurai, “Power distribution analysis of VLSI interconnects using model order reduction,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 21, no. 6, pp. 739-745, June 2002.paper
Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Youngsoo Shin, and Takayasu Sakurai, “A controller LSI for realizing Vdd-hopping scheme with off-the-shelf processors and its application to MPEG4 system,” IEICE Transactions on Electronics, vol. E58-C, no. 2, pp. 263-271, Feb. 2002.paper
Youngsoo Shin, Kiyoung Choi, and Young-Hoon Chang, “Narrow bus encoding for low-power DSP systems,” IEEE Transactions on Very Large Scale Integration Systems, vol. 9, no. 5, pp. 656-660, Oct. 2001.paper
Youngsoo Shin, Kiyoung Choi, and Takayasu Sakurai, “Power-conscious scheduling for real-time embedded systems design,” VLSI Design: An Int'l Journal of Custom-Chip Design, Simulation, and Testing, vol. 12, no. 2, pp. 139-150, 2001.paper
Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, “Partial bus-invert coding for power optimization of application-specific systems,” IEEE Transactions on Very Large Scale Integration Systems, vol. 9, no. 2, pp. 377-383, Apr. 2001.paper
Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, “Reduction of bus transitions with partial bus-invert coding,” IEE Electronics Letters, vol. 34, no. 7, pp. 642-643, Apr. 1998.paper
Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, and Kiyoung Choi, “An integrated cosimulation environment for heterogeneous systems prototyping,” Design Automation for Embedded Systems, vol. 3, issue 2/3, pp. 163-186, Mar. 1998, Kluwer Academic Publishers.paper
Note Many of the papers above have been made available for easy access. Please be aware that they are copyrighted by the organization responsible for the corresponding conference or journal.
