Wachirawit Ponghiran (Mint)
M.S. candidate, μComputing Lab., EE, KAIST

291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: wponghiran at gmail.com
Office: NanoSoC S-204



Educations
  • Mahidol Wittayanusorn School, Thailand (2009.3 - 2011.3)
  • KAIST, Department of Electrical Engineering B.S. (2011.8 - 2015.8)
  • KAIST, Department of Electrical Engineering M.S. (2015.8 - Present)
Research Interests
  • Clock tree synthesis and optimization
  • Design for manufacturability (DFM)
  • Low-power design
Publications
  • Conference Papers
    1. Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin, "Clock tree optimization through selective airgap insertion," Proc. Int'l Symp. on Quality Electronic Design (ISQED), Mar. 2017.