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Woohyun Chung (정우현)
Ph.D candidate, μComputing Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: wh.chung at kaist.ac.kr
Office: NanoSoC S-204
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Personal Information
- Date of Birth: March 6th, 1990
- Place of Birth: Seoul, Korea
- Hobbies: Electric Guitar, Motorcycle, Coffee
Educations
- Youngdong High School (2006.3 ~ 2009.2)
- KAIST, Dept. of Electrical Engineering B.S. (2009.2 ~ 2013.8)
- KAIST, Dept. of Electrical Engineering M.S. (2013.8 ~ 2014.8)
- KAIST, Dept. of Electrical Engineering M.S. & Ph.D combined course (2014.8 ~)
Research Interests
- Design for manufacturability (DFM)
- Lithography-aware physical design
- CAD for directed self-assembly lithography (DSAL)
- Latch placement optimization
Research Experience
- IBM T.J. Watson Research Center, Contractor (Jan. ~ Jul., 2016)
- LG Electronics, Visiting researcher (Mar. ~ Jul., 2014)
Publications
- Journal Papers
- Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Lithography defect probability and its application to physical design optimization,” IEEE Transactions on CAD of Integrated Circuits and Systems, under review.
- Conference Papers
- Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Redundant via insertion for multiple-patterning directed-self-assembly lithography," Proc. Design Automation Conf. (DAC), June 2016.
- Woohyun Chung, Seongbo Shim, and Youngsoo Shin, "Redundant via insertion in directed self-assembly lithography," Proc. Design, Automation & Test in Europe (DATE), Mar. 2016.
- Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Defect probability of directed self-assembly lithography: fast identification and post-placement optimization," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), Nov. 2015.
- Woohyun Chung, Seongbo Shim, and Youngsoo Shin, "Identifying redundant inter-cell margins and its application to reducing routing congestion," Proc. Design, Automation & Test in Europe (DATE), pp. 1659-1664, Mar. 2015.
- Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Synthesis of lithographic test patterns through topology-oriented pattern extraction and classification," Proc. SPIE Advanced Lithography, pp. 1-10, Feb. 2014.
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