https://sites.google.com/site/kaistshinlab/members_sbshim/SeongboShim2.jpg?attredirects=0
Seongbo Shim Ph.D. (심성보)

291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: shim47.shim at samsung.com; sbshim at kaist.ac.kr
Office: NanoSoC S-204



EDUCATION:
  • Seoul National University, Dept. of Physics B.S. (2000.3 ~ 2004.8)
  • Seoul National University, Dept. of Physics M.S. (2004.9 ~ 2006.8) 
  • KAIST, School of Electrical Engineering Ph.D. (2013.3 ~ 2016.8) 

WORK EXPERIENCE:
  • Assistant EngineerSamsung Electronics, Semiconductor R&D Center (2006.8 ~ 2009.2) 
  • EngineerSamsung Electronics, Semiconductor R&D Center (2009.3 ~ 2012.2)
  • Staff EngineerSamsung Electronics, Semiconductor R&D Center (2012.3 ~ 2019.2)
  • Principal EngineerSamsung Electronics, Semiconductor R&D Center (2019.3 ~ present)

AWARDS AND HONORS:

  • Early Promotions: 1-year-early promotion to principal engineer (2019.2) and staff engineer (2012.2), Samsung Electronics, Semiconductor R&D Center
  • SEC Annual Awards, the 1st place (2019.1)
    • Awarded by President of SEC Semiconductor R&D Center to top 10 engineers of the R&D Center in year 2018
  • SEC Annual Awards, the 3rd place (2018.1)
    • Awarded by President of SEC Semiconductor R&D Center to top 10 engineers of the R&D Center in year 2017
  • Outstanding Ph.D. Dissertation Award (2017.01)
    • Awarded by KAIST President to one Ph.D. graduate out of all graduates of EE department in year 2016
  • Travel grant award at SIGDA Ph.D Forum, DAC 2016 (2016.06)
  • Travel grant award at ACM student research competition (SRC), ICCAD (2014.11, 2015.11)
  • Travel grant award at SIGDA student research forum, ASP-DAC (2015.01)
  • Richard newton young fellow award, DAC (2013.06)
  • Scholarship awarded by Lotte foundation (Apr. 2006)

PROFESSIONAL ACTIVITIES:

  • Publicity chair: ASPDAC 2018  
  • Special session organizer: VLSI-SoC (2015.10, 2017.10)
  • TPC member: VLSID 2016
  • Invited talks: Next generation lithography conference (2015.04, 2016.04, 2017.07), VLSI-SoC (2015. 10), ICICDT (2016. 06), APCCAS (2016.10)
RESEARCH INTERESTS:
  • Extreme ultra violet lithography (EUVL): scanner system and computational lithography
  • Machine learning for lithography optimization
  • Directed self-assembly lithography (DSAL): computational lithography and CAD  
  • Design for manufacturability (DFM), lithography-aware physical design
  • Mask synthesis and optical proximity correction (OPC) 
  • Clock tree synthesis with mesh and crosslink
  • Thermal analysis 
  • Neuromorphic

TUTORIAL AND SHORT COURSE:
  1. “Directed Self-Assembly Lithography (DSAL): Mask Synthesis and Circuit Design,” tutorial delivered at Asia South Pacific Design Automation Conf. (ASP-DAC), Jan 25, 2016, Macao. 
  2. Lectures in Samsung Electronics (2009.3 ~ present)
    • OPC (basic and expert level courses for engineers in semiconductor R&D center and memory division)
    • Photolithography (basic and expert level courses for engineers in semiconductor R&D center)
    • Computational patterning  (for engineers in semiconductor R&D center)

PUBLICATION:
  • International Journal Paper:
      1. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Neural network classifier-based OPC with imbalanced training data," IEEE Transactions on CAD of Integrated Circuits and Systems, accepted for publication.
      2. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Electrothermal analysis with non-convective boundary conditions," IEEE Transactions on Circuits and Systems II, accepted for publication.
      3. Seongbo Shim and Youngsoo Shin, "Machine learning-guided etch proximity correction," IEEE Transactions on Semiconductor Manufacturing, vol. 30, no. 1, pp. 1-7, Feb. 2017. PDFpaper
      4. Seongbo Shim and Youngsoo Shin, “Fast verification of guide patterns for directed self-assembly lithography," IEEE Transactions on CAD of Integrated Circuits and Systems, accepted for publication.
      5. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, "Light interference map: a prescriptive optimization of lithography-friendly layout,"  IEEE Transactions on Semiconductor Manufacturing, vol. 29, pp.44-49, Feb. 2016PDFpaper
      6. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, “Lithography defect probability and its application to physical design optimization,” IEEE Transactions on Very Large Scale Integration Systems, vol. 25, no. 1, pp. 271-285, Jan. 2017. PDFpaper
      7. Seongbo Shim, Jae Wook Lee, and Youngsoo Shin, "An analytical approach to thermal design and optimization with a temperature-dependent power model," IEEE Transactions on Circuits and Systems I, vol. 62, no. 3, pp. 1-9, Mar. 2015. PDFpaper
      8. Seongbo Shim and Youngsoo Shin, "Topology-oriented pattern extraction and classification for synthesizing lithography test patterns," Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 14(1), no. 013503, pp. 1-12, Jan. 2015. PDFpaper
      9. Moonseok Kim, Sukjoon Hong, Seongbo Shim, Kwangsup Soh, Younghun Yu, Sanghoon Shin, Jaewan Kim, Jaisoon Kim, “Twin-image elimination using quadrantal masks in a digital holographic microscope,” Optical Engineering, vol. 50, no. 2, pp. 025801-025801-6, Feb. 2011.
      10. Moonseok Kim, Sukjoon Hong, Seongbo Shim, Kwangsup Soh, Sanghoon Shin, Jung-Young Son, Jaesung Lee, Jaisoon Kim, “Plane wave illumination for correct phase analysis and alternative phase unwrapping in dual-type (transmission and reflection) three-dimensional digital holographic microscopy,” Optical Engineering, vol. 49, no. 05, pp. 055801-055801-7, May 2010.
    • International Conference Paper:
      1. Wachirawit Ponghiran, Seongbo Shim, and Youngsoo Shin, "Cut mask optimization for multi-patterning directed self-assembly lithography", Proc. Design, Automation & Test in Europe (DATE), Mar. 2017.
      2. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, "Machine learning-based 3D resist model," Proc. SPIE Advanced Lithography, Feb. 2017.
      3. Seongbo Shim, Suhyeong Choi, and Youngsoo Shin, "Machine learning (ML)-based lithography optimization," Proc. Asia Pacific Conf. on Circuits and Systems (APCCAS), Oct. 2016.
      4. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Placement optimization for MP-DSAL compliant layout,"Proc. Int'l Conf. on IC Design & Technology (ICICDT), June 2016.
      5. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Redundant via insertion for multiple-patterning directed-self-assembly lithography," Proc. Design Automation Conf. (DAC), June 2016.
      6. Kiwon Yoon, Seongbo Shim, and Youngsoo Shin, "Crosslink insertion for minimizing OCV clock skew," Proc. IEEE Int'l Symp. on Circuits and Systems (ISCAS), May 2016.
      7. Woohyun Chung, Seongbo Shim, and Youngsoo Shin, "Redundant via insertion in directed self-assembly lithography," Proc. Design, Automation & Test in Europe (DATE), Mar. 2016. 
      8. Seongbo Shim and Youngsoo Shin, "Etch proximity correction through machine-learning-driven etch bias model," Proc. SPIE Advanced Lithography, Feb. 2016.
      9. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Machine learning (ML)-guided OPC using basis functions of polar Fourier transform," Proc. SPIE Advanced Lithography, Feb. 2016.
      10. Seongbo Shim and Youngsoo Shin, "Mask optimization for directed self-assembly lithography: inverse DSA and inverse lithography," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2016.
      11. Seongbo Shim, Woohyun Chung, and Youngsoo Shin, "Defect probability of directed self-assembly lithography: fast identification and post-placement optimization," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), Nov. 2015.
      12. Suhyeong Choi, Seongbo Shim, and Youngsoo Shin, "Electrothermal analysis with generalized boundary conditions," Proc. Int'l SoC Design Conf. (ISOCC), Nov. 2015.
      13. Seongbo Shim and Youngsoo Shin, "Physical design and mask optimization for directed self-assembly lithography (DSAL)," Proc. Int'l Conf. on Very Large Scale Integration (VLSI-SoC), Oct. 2015. 
      14. Woohyun Chung, Seongbo Shim, Inhak han, and Youngsoo Shin, "Identifying redundant inter-cell margins and its application to reducing routing congestion," Proc. Design, Automation & Test in Europe (DATE), Mar. 2015.
      15. Seongbo Shim, Sibo Cai, Jaewon Yang,  Seunghune Yang, Byungil Choi, and Youngsoo Shin, "Verification of direct self-assembly (DSA) guide patterns through machine learning," Proc. SPIE Advanced Lithography, Mar. 2015.
      16. Seongbo Shim and Youngsoo Shin, "Synthesis of lithographic test patterns through topology-oriented pattern extraction and classification," Proc. SPIE Advanced Lithography, Feb. 2014.
      17. Seongbo Shim, Yoojong Lee, and Youngsoo Shin, "Lithographic defect aware placement using compact standard cells without inter-cell margin," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2014.
      18. Seongbo Shim, Minyoung Mo, Sangmin Kim, and Youngsoo Shin, "Analysis and minimization of short-circuit current in mesh clock network," Proc. Int'l Conf. on Computer Design (ICCD), Oct. 2013.
      19. Seung-Hune Yang, Ningning Jia, Seongbo Shim, Dmitry Vengertsev, Jungdal Choi, Ho-Kyu Kang, Young-Chang Kim, “The effect of mask and source complexity on source mask optimization,” Proc. SPIE Advanced Lithography, pp. 1-9, Apr. 2013.
      20. Dmitry Vengertsev, Kihyun Kim, Seung-Hune Yang, Seongbo Shim, Seongho Moon, Artem Shamsuarov, Sooryong Lee, Seong-Woon Choi, Jungdal Choi, Ho-Kyu Kang, “The new test pattern selection method for OPC model calibration, based on the process of clustering in a hybrid space,” Proc. SPIE Photomask Technology, pp. 1-8, Nov. 2012.
      21. Seongbo Shim, Seongho Moon, Youngchang Kim, Seongwoon Choi, Younghee Kim, Bernd Küchler, Ulrich Klostermann, Munhoe Do, Sooryoung Lee, “Physical simulation for verification and OPC on full chip level,” Proc. SPIE Advanced Lithography, pp. 1-9, Apr. 2011.
      22. Jeong-Geun Park, Sang-wook Kim, Seongbo Shim, Sung-Soo Suh, Hye-Keun Oh, “The effective etch process proximity correction methodology for improving on chip CD variation in 20nm node DRAM gate,” Proc. SPIE Advanced Lithography, pp. 1-10, Apr. 
      23. Moon-Gyu Jeong, Won-Chan Lee, Seung-Hune Yang, Sung-Hoon Jang, Seongbo Shim, Young-Chang Kim, Chun-Suk Suh, Seong-Woon Choi, Young-Hee Kim, “Investigating the performance of directional boundary layer model through staged modeling method,” Proc. SPIE Advanced Lithography, pp. 1-9, Mar. 2011.
      24. Seongbo Shim, Young-chang Kim, Seong-hoon Jang, Hee-bom Kim, Sung-woo Lee, Seong-woon Choi, Han-ku Cho, Chan-hoon Park, “Development and evaluation of new MRC parameter for aggressive mask optimization,” Proc. SPIE Lithography Asia, pp. 1-9, Dec. 2009.
      25. Seongbo Shim, Young-chang Kim, Yong-jin Chun, Seong-Woo Lee, Suk-joo Lee, Seong-woon Choi, Woo-sung Han, Seong-hoon Chang, Seok-chan Yoon, Hee-bom Kim, Won-tai Ki, Sang-gyun Woo, Han-gu Cho, “Optimization of mask manufacturing rule check constraint for model based assist feature generation,” Proc. SPIE Lithography Asia, pp. 1-9, Dec. 2008.
      26. Seongbo Shim, Young-chang Kim, Suk-joo Lee, Seong-woon Choi, Woo-sung Han, “Study of the mask topography effect on the OPC modeling of hole patterns,” Proc. SPIE Advanced Lithography, pp. 1-8, Apr. 2008.
      27. Mi-Rim Jung, Eun-A Kwak, Hye-Keun Oh, Seongbo Shim, Na-Rak Choi, Jai-Soon Kim, “Evaluation of partial coherent imaging using the transfer function in immersion lithography,” Proc. SPIE Advanced Lithography, pp. 1-8, Apr. 2006.
    • Domestic Publication:
      1. 심성보, "Machine learning-guided 3-D resist model," 2017 차세대 리소그라피 학술대회, 2017년 7월. 
      2. 최수형, 심성보, 신영수, "Full-chip level estimation of temperature-dependent leakage power," 제24회 한국반도체학술대회, 2017년 2월.
      3. 심성보, "Machine learning for computational lithography,", 2016 차세대 리소그라피 학술대회, 2016년 4월. 
      4. 정우현, 심성보, 신영수, "Automatic placement for directed self-assembly lithography," 제23회 한국반도체학술대회, 2016년 2월.
      5. 심성보, "Layout coverage analysis through topology-oriented pattern extraction and classification,"  2015 차세대 리소그라피 학술대회, 2015년 4월.
      6. 정우현, 심성보, 신영수, "Reducing routing congestion and chip area by post placement optimization utilizing redundant inter-cell margin,"제22회  한국반도체학술대회, 2015년 2월.
      7. 이유종, 심성보, 신영수, "Identifying redundant inter-cell margins and its application to technology mapping," 제21회 한국반도체학술대회, 2014년 2월.
    • Patents: filed 14 US