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Kiwon Yoon (윤기원)
Ph.D. candidate, μComputing Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: antiares at kaist.ac.kr
Office: NanoSoC S-204
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Personal Information
- Date of Birth: May 30th, 1989
- Place of Birth: Seoul, Korea
- Interests: EDM
Educations
- Suji High School (2005.3 ~ 2008.2)
- Yonsei University, Dept. of Electrical Engineering B.S. (2008.3 ~ 2014.2)
- KAIST, Dept of Electrical Engineering M.S. (2014.9 ~ 2016.8)
- KAIST, Dept of Electrical Engineering Ph.D. (2016.9 ~)
Research Interests
- Clock tree synthesis with crosslink
- Low power design of dual-mode circuit
- Brain-inspired neuromorphic hardware
Publications
- Conference Papers
- Kiwon Yoon, Seongbo Shim, and Youngsoo Shin, "Crosslink insertion for minimizing OCV clock skew," Proc. Int'l Symp. on Circuits and Systems (ISCAS), pp. 2587-2590, May 2016.
- Kiwon Yoon, Suhyeong Choi, and Youngsoo Shin, "Area efficient neuromorphic circuit based on stochastic computation," Proc. Int'l SoC Design Conf. (ISOCC), pp. 73-74, Oct. 2016.
- Kiwon Yoon, Daijoon Hyun, and Youngsoo Shin, "Fast timing analysis of non-tree clock network with shorted wires," Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 279-284, May 2018.
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