Jinwook Jung (정진욱)
Ph.D. candidate, μComputing Lab., EE, KAIST

291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: jinwookjung at kaist.ac.kr
Office: NanoSoC S-204



Personal Information
  • Date of birth: July 12th, 1987
  • Place of birth: Daegu, Korea
  • Hobbies: Photography
  • Personal web site: Link

Educations
  • KAIST, Dept. of Electrical Engineering Ph.D. (Sept. 2013 - )
  • Kobe University, Graduate School of System Informatics M.E. (Apr. 2011 - Mar. 2013) 
  • Kobe University, Dept. of Computer Science and System Engineering B.E. (Apr. 2007 - Mar. 2011)
  • High School Attached to College of Education, Choong-Ang University (Mar. 2003 - Feb 2006) 

Research Experience

  • IBM T. J. Watson Research Center, Research scholar (Feb. 2017 - May 2017)
  • IBM T. J. Watson Research Center, Research scholar (July 2015 - Dec. 2015)
  • LG Electronics, Visiting researcher (July 2013 - Feb. 2014)
  • Kobe University, Research assistant (Sept. 2011 - Mar. 2012)

Honors
  • Student Travel Grant at the 2016 ICCAD (Nov. 2016)
  • 2015 Annual Honor Roll Award (KAIST)
  • IEEE Circuits & Systems Society Student Travel Award 2014 (Oct. 2014)
  • Richard Newton Young Fellow Award at the 51th DAC (June 2014)
  • Student Commencement Speaker and Representative of Graduating Class (Kobe University) (Mar. 2013)
  • Distinguished Graduate Student Award (Kobe University) (Mar. 2013)
  • Rotary Yoneyama Memorial Master Course Scholarship (Apr. 2012 - Mar. 2013)
  • Korea-Japan Joint Government Scholarship (Five-year full scholarship) (Mar. 2006 - Mar. 2011)

Research Interests
    • VLSI physical design
    • Design automation

    Publications
    • Journal Papers
      1. Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, "OWARU: Free Space-Aware Timing-Driven Incremental Placement with Critical Path Smoothing," IEEE Transactions on CAD of Integrated Circuits and Systems, under review.
      2. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, and Masahiko Yoshimoto,  "A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation," IEICE Trans. Electronics, vol. E97-C, no. 4, pp. 332-341, Apr. 2014.
      3. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, "Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM," IEICE Trans. Electronics, vol. E96-C, no. 4, pp.528-537, Apr. 2013.
    • Conference Papers
      1. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, "Redundant Via Insertion in SADP Process with Cut Merging and Optimization," in Proceedings of the 25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2017.
      2. Jaewoo Seo, Jinwook Jung, and Youngsoo Shin, "Pin Accessibility-driven Cell Layout Redesign and Placement Optimization," in Proceedings of Design Automation Conference (DAC), June 2017.
      3. Youngsoo Song, Jinwook Jung, and Youngsoo Shin, "Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning," in Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), May 2017.
      4. Youngsoo  Song, Jinwook Jung, and Youngsoo Shin, "Redundant Via Insertion in Self-Aligned Double Patterning," in Proceedings of SPIE Advanced Lithography, Feb. 2017.
      5. Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, and Yih-Lang Li “OpenDesign Flow Database: The Infrastructure for VLSI Design and Design Automation Research,” in Proceedings of the 2016 International Conference on Computer-Aided Design (ICCAD), Nov. 2016.
      6. Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, and Youngsoo Shin, "OWARU: Free Space-Aware Timing-Driven Incremental Placement," in Proceedings of the 2016 International Conference on Computer-Aided Design (ICCAD), Nov. 2016.
      7. Jinwook Jung and Youngsoo Shin, "Localized DNA Circuit Design with Majority Gates," in Proceedings of the 12th BioMedical Circuits and Systems Conference (BioCAS), Oct. 2016.
      8. Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, "Physical Synthesis of DNA Circuits with Spatially Localized Gates," Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD), Oct. 2015.
      9. Jinwook Jung, Dongsu Lee, and Youngsoo Shin, "Design and Optimization of Multiple-Mesh Clock Network," in Proceedings of the 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2014, pp. 171-176.
      10. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, and Masahiko Yoshimoto, "A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement," in Proceedings of the 15th International Symposium on Quality Electronic Design (ISQED), Mar. 2014, pp.16-23.
      11. Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, and Hiroshi Kawaguchi, "Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting All-Zero-Data Flags," in Proceedings of the 14th International Symposium on Quality Electronic Design (ISQED), Mar. 2013, pp.216-222.
      12. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi and Masahiko Yoshimoto, "A Variation-Aware 0.57-V Set-Associative Cache with Mixed Associativity Using 7T/14T SRAM," in Proceedings of the 11th IEEE Faible Tension Faible Consommation (IEEE FTFC), June 2012, pp.1-4.
      13. Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi and Masahiko Yoshimoto, "256-KB Associativity-Reconfigurable Cache with 7T/14T SRAM for Aggressive DVS Down to 0.57 V," in Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems (IEEE ICECS), Dec. 2011, pp.524-527.
    • Patents
      1. Hiroshi Kawaguchi, Masahiko Yoshimoto, Yohei Nakata, and Jinwook Jung, "Nonvolatile Memory Cache," Japanese patent 2014-153965, Feb. 11, 2013.
      2. Masahiko Yoshimoto, Hiroshi Kawaguchi, Yohei Nakata, Shunsuke Okumura, and Jinwook Jung, "Low-Voltage Cache with Mixed-Associativity," Japanese patent 2016-6024897.
    • Books
      1. Jinwook Jung, Dongsoo Lee, and Youngsoo Shin, "Design and Optimization of Multiple-Mesh Clock Network," Chapter 3, VLSI-SoC: Internet of Things Foundations, Springer, 2015.