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Jingon LEE (이진곤)
M.S. candidate, μComputing Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea Phone: +82-42-350-5479 / Fax: +82-42-351-9895 Email: ljg1501 at kaist.ac.kr
Office: NanoSoC S-204
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Personal Information
- Date of Birth: May 22, 1991
- Place of Birth: Suwon, Korea
- Hobbies: Bicycle riding, basketball
Education
- HyoWon High school (Mar. 2007 - Feb. 2010)
- KyungHee university, School of Electrical and information Engineering B.S.
(Mar. 2010 - Feb. 2017)
- KAIST, School of Electrical Engineering M.S. (Mar. 2017 - Feb. 2019)
Research Interests
- Circuit timing analysis
- CMOS manufacture process
Publications
- Journal Papers
- Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, and Youngsoo Shin, "Cut optimization for redundant via insertion in self-aligned double patterning," ACM Transactions on Design Automation of Electronic Systems, accepted for publication.
- Jingon Lee, jinwook Jung, and Youngsoo Shin, "Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits," Proc. Int'l Symp. on Circuits and Systems (ISCAS), May 2018.
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