Inhak Han (한인학)
Post Doctoral Researcher, μComputing Lab., EE, KAIST

291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: drct1225 at
Office: NanoSoC S-204

Personal Information
  • Date of Birth: June 10th, 1987
  • Place of Birth: Namwon, Korea
  • Hobbies: basketball

  • Seoul Science High School (2003.3 ~ 2005.2)
  • KAIST, Dept. of Electrical Engineering B.S. (2005.3 ~ 2010.2)
  • KAIST, Dept. of Electrical Engineering M.S. (2010.2 ~ 2012.2)
  • KAIST, Dept. of Electrical Engineering Ph.D. (2012.2 ~ 2017.6)

Miscellaneous Experiences
  • Internship @ IBM ARL (2011.07~2011.10)
  • Richard Newton Young Fellow Award at the 50th DAC (2013.06)
  • Internship @ LGE (2013.10~2014.04)
  • Internship @ Samsung Electronics (2015.07~2015.08)

Research Interests
  • Timing analysis
  • Thermal analysis
  • Logic synthesis
  • Pulsed latch circuits
  • Clock gating
  • Dual edge-triggered flip-flop

  • Journal Papers
    1. I. Han and Y. Shin, "Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops," ACM ToDAES, vol. 23, no. 5, pp. 61:1-61:21, Aug. 2018. PDF.gifpaper
    2. I. Han and Y. Shin, "Simplifying clock gating logic by matching factored forms," IEEE TVLSI, vol. 22, no. 6, pp. 1338-1349, June 2014. PDF.gifpaper
    3. S. Paik, I. Han, S. Kim, and Y. Shin, "Clock gating synthesis of pulsed-latch circuits," IEEE TCAD, vol. 31, no. 7, pp. 1019-1030, July 2012. PDF.gifpaper
  • Conference Papers
    1. Y. Kwon, J. Jung, I. Han, and Y. Shin "Transient clock power estimation of pre-CTS netlist," ISCAS, May 2018. PDF.gifpaper
    2. I. Han, J. Kim, J. Yi, and Y. Shin "Register grouping for synthesis of clock gating logic," ICICDT, June 2016. PDF.gifpaper
    3. I. Han, D. Hyun, and Y. Shin, "Buffer insertion to remove hold violations at multiple process corners,"  Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2016. PDFpaper
    4. I. Han and Y. Shin "Folded circuit synthesis: logic simplification using dual edge-triggered flip-flops," ICICDT, May 2013. PDF.gifpaper
    5. I. Han and Y. Shin "Synthesis of clock gating logic through factored form matching," ICICDT, May 2012. PDF.gifpaper
    6. J. Kung, I. Han, and Y. Shin "Thermal signature: a simple yet accurate thermal index for floorplan optimization," DAC, June 2011. PDF.gifpaper
    7. S. Kim, I. Han, S. Paik, and Y. Shin, "Pulser gating: a clock gating of pulsed-latch circuits," ASPDAC, Jan. 2011. PDF.gifpaper
    8. I. Han, L. Yu, and Y. Shin "Fast monte carlo method via reduced sample number and node filtering," Proc. ICICDT, June 2010. PDF.gifpaper