PH.D. candidate, VLSI Design Technology Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 305-701, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: dkbaek at ee.kaist.ac.kr
Office: NanoSoC S-204
- Date of Birth: July 21th, 1984
- Place of Birth: Seoul, Korea
- Hobbies: singing, table tennis
- Daeyoung High School (2000.3 ~ 2003.2)
- Hanyang University, Dept. of Electrical Engineering B.S. (2003.3 ~ 2008.8)
- KAIST, Dept. of Electrical Engineering M.S. (2009.2 ~ 2011.1)
- KAIST, Dept. of Electrical Engineering PH.D. (2011.2 ~ )
- Structured ASIC
- Body-Biased Gate Delay Modeling
- Pulsed-VDD Circuit Design
- Donkyu Baek, Insup Shin, and Youngsoo Shin, "Accurate gate delay extrapolation for timing analysis of body-biased circuits," IEEE Transaction on Very Large Scale Integration Systems, submitted, Aug. 2012.
- Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, and Seungwhun Paik, "HAPL:heterogeneous array of programmable logic using selective mask patterning," IEEE Transaction on Circuits and Systems I, submitted, July 2012.
- Donkyu Baek, Insup Shin, and Youngsoo Shin, "Gate delay modeling for static timing analysis of body-biased circuits," Proc. Int'l Conference on IC Design & Technology (ICICDT), May. 2012.
- Donkyu Baek, Insup Shin, Seungwhun Paik, and Youngsoo Shin, "Selectively patterned masks: structured ASIC with asymptotically ASIC performance," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp.376-381, Jan. 2011.
- Donkyu Baek, Insup Shin, Seungwhun Paik, and Youngsoo Shin, "Selectively patterned masks: beyond structured ASIC," Proc. Int'l SoC Design Conf. (ISOCC), pp. 154-157, Nov. 2010.