Daijoon Hyun (현대준)
Ph.D. candidate, μComputing Lab., EE, KAIST

291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: ars0130 at
Office: NanoSoC S-204

Personal Information
  • Date of Birth: January 30th, 1980
  • Place of Birth: Seoul, Korea
  • Hobbies: Badminton, Golf, Yoga

  • Seoul High School (Mar. 1995 - Feb. 1998)
  • Hanyang University, Dept. of Electrical Engineering B.E. (Mar. 1999 - Feb. 2006)
  • Pohang University of Science and Technology, Dept. of Electrical Engineering M.E. (Mar. 2006 - Feb. 2008)
  • System LSI Business, Samsung Electronics (Aug. 2008 - Feb. 2015)
  • KAIST, Dept. of Electrical Engineering Ph.D. (Mar. 2015 - Aug. 2019)
  • Foundry Business, Samsung Electronics (Sep. 2019 -)

Experiences and Honors
  • Student research competition (SRC) @ ICCAD: Finalist (Nov. 2018)
  • 우수발표논문상 @ SoC 학술대회: 2nd author (May 2018)
  • Student research forum (SRF) @ ASPDAC (Jan. 2017)
  • Best paper award @ ISOCC (Nov. 2015)
  • Internship @ FineSim team of Magma-DA (Dec. 2007 - Jun. 2008)
  • Research Assistant @ POSTECH (Mar. 2007 - Aug. 2007)

Research Interests

    • Design methodology for advanced technology: airgap, SADP, SIV, etc.
    • Machine-learning for computer-aided design
    • Model-to-hardware correlation (MHC) based design methodology
    • Near threshold voltage (NTV) design
    • Interconnect corner modeling

    • Journal Papers
      1. Daijoon Hyun, Younggwang Jung, and Youngsoo Shin, "Selective use of stitch-induced via for V0 mask reduction: standard cell design and placement optimization," IEICE Transactions on Fundamentals of Electonics, Communications and Computer Sciences, accepted for publication.
      2. Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, and Youngsoo Shin, "Cut optimization for redundant via insertion in self-aligned double patterning." ACM Transactions on Design Automation of Electronic Systems, accepted for publication.
      3. Daijoon Hyun and Youngsoo Shin, "Integrated approach of airgap insertion for circuit timing optimization," ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 2, pp. 24:1-24:22, Feb. 2019.
    • Conference Papers
      1. Younggwang Jung, Daijoon Hyun, and Youngsoo Shin, "Integrated airgap insertion  and layer reassignment for circuit timing optimization," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2020, accepted for publication.
      2. Daijoon Hyun, Yuepeng Fan, and Youngsoo Shin, "Accurate wirelength prediction for placement-aware synthesis through machine learning," Proc. Design, Automation & Test in Europe (DATE), pp. 324-327, Mar. 2019.
      3. Kiwon Yoon, Daijoon Hyun, and Youngsoo Shin, "Fast timing analysis of non-tree clock network with shorted wires," Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 279-284, May 2018.
      4. Daijoon Hyun, Jaewoo Seo, and Youngsoo Shin, "Library optimization for near threshold voltage design," Proc. Int'l Symp. on Circuits and Systems (ISCAS), pp. 1-4, May 2018.
      5. Youngsoo Song, Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, "Timing optimization in SADP process through wire widening and double via insertion," Proc. SPIE Advanced Lithography, pp. 105880R-1-105880R-8, Feb. 2018.
      6. Daijoon Hyun and Youngsoo Shin, "Automatic insertion of airgap with design rule constraints," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 381-386, Jan. 2018
      7. Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin, "Clock tree optimization through selective airgap insertion," Proc. Int'l Symp. on Quality Electronic Design (ISQED), pp. 203-208, Mar. 2017.
      8. Daijoon Hyun and Youngsoo Shin, "Selection of airgap layers for circuit timing optimization," Proc. SPIE Advanced Lithography, pp. 101480O-1-101480O-8, Feb. 2017.
      9. Daijoon Hyun and Youngsoo Shin, "Modeling interconnect corners under double patterning misalignment," Proc. SPIE Advanced Lithography, pp. 97810F-1-97810F-7, Feb. 2016.
      10. Daijoon Hyun and Youngsoo Shin, "Calibration of interconnect corners using on-chip ring oscillators," Proc. Int'l SoC Design Conf. (ISOCC), pp. 39-40, Nov. 2015. (Best Paper Award)
      11. Inhak Han, Daijoon Hyun, and Youngsoo Shin, "Buffer insertion to remove hold violations at multiple process corners,"  Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 232-237, Jan. 2016.
      12. Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, "Physical synthesis of DNA circuits with spatially localized gates," Proc. Int'l Conf. on Computer Design (ICCD), pp. 280-286, Oct. 2015.