Daijoon Hyun (현대준)
Ph.D. candidate, μComputing Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: ars0130 at gmail.com
Office: NanoSoC S-204
- Date of Birth: January 30th, 1980
- Place of Birth: Seoul, Korea
- Hobbies: Badminton, Golf
- Seoul High School (Mar. 1995 - Feb. 1998)
- Hanyang University, Dept. of Electrical Engineering B.E. (Mar. 1999 - Feb. 2006)
- Pohang University of Science and Technology, Dept. of Electrical Engineering M.E. (Mar. 2006 - Feb. 2008)
- System LSI Business, Samsung Electronics (Aug. 2008 ~)
- KAIST, Dept. of Electrical Engineering Ph.D. (2015.3 - )
- Internship @ Magma-DA (Dec. 2007 - Jun. 2008)
- Process monitoring method
- Model-to-Hardware Correlation (MHC) based design methodology
- Timing analysis and optimization
- Clock tree synthesis and optimization
- Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin, "Clock tree optimization through selective airgap insertion," Proc. Int'l Symp. on Quality Electronic Design (ISQED), Mar. 2017.
- Daijoon Hyun and Youngsoo Shin, "Selection of airgap layers for circuit timing optimization," Proc. SPIE Advanced Lithography, Feb. 2017.
- Daijoon Hyun and Youngsoo Shin, "Modeling interconnect corners under double patterning misalignment," Proc. SPIE Advanced Lithography, Feb. 2016.
- Daijoon Hyun and Youngsoo Shin, "Calibration of interconnect corners using on-chip ring oscillators," Proc. Int'l SoC Design Conf. (ISOCC), Nov. 2015.
- Inhak Han, Daijoon Hyun, and Youngsoo Shin, "Buffer insertion to remove hold violations at multiple process corners," Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2016.
- Jinwook Jung, Daijoon Hyun, and Youngsoo Shin, "Physical synthesis of DNA circuits with spatially localized gates," Proc. Int'l Conf. on Computer Design (ICCD), Oct. 2015.