Post-Doctoral Researcher, μComputing Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: sangminkim at kaist.ac.kr
Office: NanoSoC S-204
- Date of Birth: September 14th, 1985
- Place of Birth: Seoul, Korea
- Hobbies: Playing games, listening to music
- Kwangnam Elementary School (1998.2)
- Chungwoon Middle School (2001.2)
- Kyungbook High School (2001.3 ~ 2004.2)
- KAIST, Dept. of Electrical Engineering B.S. (2004.3 ~ 2008.2)
- KAIST, Dept. of Electrical Engineering M.S. (2008.2 ~ 2010.2)
- KAIST, Dept. of Electrical Engineering Ph.D. (2010.2 ~ 2016.2)
- KAIST, Dept. of Electrical Engineering Post-Doctoral Researcher (2016.2 ~ )
- S. Kim, S. Kang, and Y. Shin, “Timing optimization of dual-mode circuits through standard cell design, gate sizing, and clock tree synthesis,” ACM Trans. on Design Automation of Electronic Systems, under review.
- S. Kim, S. Paik, S. Kang, and Y. Shin, "Wakeup scheduling and its buffered tree synthesis for power gating circuits," Integration, the VLSI Journal, vol. 53, pp. 157-170, Mar. 2016.
- S. Paik, I. Han, S. Kim, and Y. Shin, “Clock gating synthesis of pulsed-latch circuits,” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 31, no. 7, pp. 1019-1030, July 2012.
- Y. Chuang, S. Kim, Y. Shin, and Y. Chang, “Pulsed-latch aware placement for timing-integrity optimization,” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 30, no. 12, pp. 1856-1869, Dec. 2011.
- S. Shim, M. Mo, S. Kim, and Y. Shin, "Analysis and minimization of short-circuit current in mesh clock network," ICCD, Oct. 2013.
- S. Kim, D. Kim, and Y. Shin, "Pulsed-latch ASIC synthesis in industrial design flow," ASPDAC, Jan. 2013.
- S. Kim, I. Han, S. Paik, and Y. Shin, "Pulser gating: a clock gating of pulsed-latch circuits," ASPDAC, Jan. 2011.
- S. Paik, S. Kim, and Y. Shin, "Wakeup synthesis and its buffered tree construction for power gating circuit designs," ISLPED, Aug. 2010.
- Y. Chuang, S. Kim, Y. Shin, and Y. Chang, "Pulsed-Latch-Aware Placement for Timing-Integrity Optimization," DAC, June 2010.
- C. Oh, S. Kim, and Y. Shin "Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating," Proc. ICICDT, May 2009.