Insup Shin(신인섭)
PH.D. candidate, VLSI Design Technology Lab., EE, KAIST

291 Daehak-ro, Yuseong-gu, Daejeon 305-701, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: isshin at ee.kaist.ac.kr
Office: NanoSoC S-204
Curriculum Vitae



Personal Information
  • Date of Birth: March 4th, 1985
  • Hobbies: Baduk, Basketball

Educations
  • Chungnam Science High School (2001.3 ~ 2003.2)
  • KAIST, Dept. of Electrical Engineering B.S. (2003.3 ~ 2007.2)
  • KAIST, Dept. of Electrical Engineering M.S. (2007.3 ~2009.8)
  • KAIST, Dept. of Electrical Engineering Ph.D. (2009.9~)

Miscellaneous Experiences
  • DAC summer school (DASS) (2009.7)
  • Internship @ IBM T. J. Watson Research Center (2012.8~2012.12)

Research Interests
  • High-level synthesis
  • Structured ASIC
  • Low-power design
  • Low voltage operation

Publications
  • Journal Papers
    1. I. Shin, J.-J. Kim, Y.-S. Lin, and Y. Shin, "One-cycle correction of timing errors in pipelines with standard clocked elements," IEEE TVLSI, submitted.
    2. Y. Shin, I. Shin, D. Baek, D. Kim, and S. Paik, "HAPL: heterogeneous array of programmable logic using selective mask patterning," IEEE TCAS I, Jan. 2014.
    3. D. Baek, I. Shin, and Y. Shin, "Accurate gate delay extraction for timing analysis of body-biased circuits," JCSC, Sep. 2013.
    4. I. Shin, S.Paik, D. Shin, and Y. Shin, "HLS-dv: a high-level synthesis framework for dual-Vdd architectures," IEEE TVLSI, Apr. 2012.
    5. J. Seomun, I. Shin, and Y. Shin, "Synthesis of Active-Mode Power-Gating Circuits," IEEE TCAD, Mar. 2012.
    6. S. Paik, I. Shin, T. Kim, and Y.Shin, "HLS-l: a high-level synthesis framework for latch-based architectures," IEEE TCAD, May 2010.
  • Conference Papers
    1. I. Shin, J.-J. Kim, and Y. Shin, "Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling," ASPDAC, Jan. 2014.
    2. I. Shin, J.-J. Kim, Y.-S. Lin, and Y. Shin, "A pipeline architecture with 1-cycle timing error correction for low voltage operations," ISLPED, Sep. 2013.
    3. I. Shin, D. Baek, and Y. Shin, "Introducing irregularity to routing architecture of structured ASIC for better routability," FPT, Dec. 2012.
    4. 4.D. Baek, I. Shin, and Y. Shin, "Gate delay modeling for static timing analysis of body-biased circuits," ICICDT, May 2012.
    5. D. Baek, I. Shin, S. Paik, and Y. Shin, "Selectively patterned masks: structured ASIC with asymptotically ASIC performance," ASPDAC, Jan. 2011.
    6. D. Baek, I. Shin, S. Paik, and Y. Shin, "Selectively patterned masks: beyond structured ASIC," ISOCC, Nov. 2010.
    7. J. Seomun, I. Shin, and Y. Shin, "Synthesis and implementation of active mode power gating circuits," DAC, June 2010.
    8. I. Shin, S. Paik, and Y. Shin, "Register allocation for high-level synthesis using dual supply voltages," DAC, July 2009.
    9. S. Paik, I. Shin, and Y. Shin, "HLS-l: high-level synthesis of high performance latch-based circuits," DATE, Apr. 2009.