Jonggyu Kim (김종규)
Researcher, μComputing Lab., EE, KAIST

291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email:  jonggyu.q at gmail.com
Office: NanoSoC S-204



Personal Information
  • Date of Birth:  September 26th, 1985
  • Place of Birth: Seoul, Korea
  • Interests:  Soccer, Singing, Swing Dancing

Educations
  • Younghoon High School (2001.3 ~ 2004.2)
  • Kwangwoon University. Dept. of Computer Engineering B.S (2004.3 ~ 2011.2)
  • Kwangwoon University. Dept. of Computer Engineering M.S & PhD (2011.3 ~ present)

Research Interests
  • High Level Power Modeling
  • ESL design
  • Low power design

Publications
  • Journal Papers
    1. Jonggyu Kim, and Joonhwan Yi. "High-level Power Modeling of Clock Gated Circuits." Journal of the Institute of Electronics and Information Engineers 52. Oct. 2015, pp. 56-63.
    2. Joonhwan Yi, and Jonggyu Kim. "Power modeling for digital circuits with clock gating." IEICE Electronics Express, Nov. 2015.
  • Conference Papers
    1. Inhak Han, Jonggyu Kim, Joonhwan, Yi, & Youngsoo Shin, “Register grouping for synthesis of clock gating logic,” In IC Design and Technology (ICICDT), 2016 International Conference on IEEE, pp. 1-4.