Seungwhun Paik
(백승훈, 白承勳)
Senior R&D engineer, Synopsys
Curriculum Vitae (as of July 2011)


Personal Information
  • Date of Birth: May 22nd, 1980
  • Place of Birth: Taegu, Korea
  • Hobbies: Basketball, Movie, Go (바둑)
  • Religion: Christianity

Educations
  • Daejon Science High School (TSHS 13th) (1996.3 ~ 1998.2)
  • KAIST, Dept. of EE B.S. (1998.3 ~ 2006.8)
  • KAIST, Dept. of EE M.S.-Ph.D Joint Program (2006.9 ~ 2011.08)

Miscellaneous Experiences
  • MicroWeb as a hardware engineer (2002.1~2002.9)
  • PDI-ATC as an application & system engineer (2002.10~2006.1)
  • H.264 Decoder chip project: intra predictor (2006.3~2006.8)
  • DAC summer school (DASS) (2007.6.2~3)
  • SIGDA CADathlon @ ICCAD (2008.11.9)
  • ACM Student Research Competition @ DAC (2010.6)
  • Internship @ IBM ARL (2010.11~2011.1)

Research Interests
  • •ABB with mixed Vt, Sleep vector optimization of ZPG circuits
  • •Pulsed-latch circuits for optimizing conventional ASIC
  • •High-level synthesis
  • •Wakeup synthesis of power-gated circuits

Publications
  • Journal Papers
    1. Y. Shin, I. Shin, D. Baek, D. Kim, and S. Paik, "HAPL: heterogeneous array of programmable logic using selective mask patterning," IEEE TCAS I, Jan 2014.
    2. S. Paik, I. Han, S. Kim, and Y. Shin, "Clock gating synthesis of pulsed-latch circuits," IEEE TCAD, July 2012.
    3. I. Shin,S. Paik, D. Shin, and Y. Shin, "HLS-dv: a high-level synthesis framework for dual-Vdd architecture," IEEE TVLSI, Apr. 2012.
    4. L. Yu, C. Shin, S. Paik, J. Liou, and Y. Shin, "Sampling correlation sources for timing yield analysis of sequential circuits with clock networks," JCSC, Dec. 2011.
    5. Y. Shin and S. Paik, "Pulsed-latch circuits: a new dimension in ASIC design," IEEE Design & Test of Computers, Nov./Dec. 2011.
    6. S. Paik, S. Lee, and Y. Shin, "Retiming pulsed-latch circuits with regulating pulse width," IEEE TCAD, Aug. 2011.
    7. S. Paik, I. Shin, T. Kim, and Y.Shin, "HLS-l: a high-level synthesis framework for latch-based architectures," IEEE TCAD, May 2010.PDF.gifpaper
    8. H. Lee, S. Paik, and Y.Shin, "Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches," IEEE TCAD, Mar. 2010.PDF.gifpaper
    9. Y. Shin, S. Paik, and H.-O. Kim, "Semicustom design of zigzag power-gated circuits in standard cell elements," IEEE TCAD, Mar. 2009.PDF.gifpaper

  • Conference Papers
    1. S. Paik, G. Nam, and Y. Shin, "Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power," ICCAD, Nov. 2011.
    2. S. Paik, J. Kung, and Y. Shin, "Exploring the opportunity of optimizing sequencing elements in ASIC designs," MWSCAS, Aug. 2011.
    3. S. Kim, I. Han, S. Paik, and Y. Shin, "Pulser gating: a clock gating of pulsed-latch circuits," ASPDAC, Jan. 2011.
    4. D. Baek, I. Shin, S. Paik, and Y. Shin, "Selectively patterned masks: structured ASIC with asymptotically ASIC performance," ASPDAC, Jan. 2011.
    5. D. Baek, I. Shin, S. Paik, and Y. Shin, "Selectively patterned masks: beyond structured ASIC," ISOCC, Nov. 2010.
    6. S. Paik and Y. Shin, "Pulsed-latch circuits to push the envelope of ASIC design," ISOCC, Nov. 2010.
    7. S. Paik, S. Kim, and Y. Shin, "Wakeup synthesis and its buffered tree construction for power gating circuit designs," ISLPED, Aug. 2010.PDF.gifpaper
    8. S. Paik, L. Yu, and Y. Shin, "Statistical Time Borrowing for Pulsed-Latch Circuit Designs," ASPDAC, Jan. 2010.PDF.gifpaper
    9. J. Seomun, S. Paik, and Y. Shin, "Bounded potential slack: enabling time budgeting for dual-vt allocation of hierarchical design," ASPDAC, Jan. 2010.PDF.gifpaper
    10. S. Lee, S. Paik, and Y. Shin, "Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits," ICCAD, Nov. 2009.PDF.gifpaper
    11. I. Shin, S. Paik, and Y. Shin, "Register allocation for high-level synthesis using dual supply voltages," DAC, July 2009.PDF.gifpaper
    12. S. Paik, I. Shin, and Y. Shin, "HLS-l: high-level synthesis of high performance latch-based circuits," DATE, Apr. 2009.PDF.gifpaper
    13. H. Lee, S. Paik, and Y. Shin, "Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits," ICCAD, Nov. 2008.PDF.gifpaper
    14. S. Paik and Y. Shin, "Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements," DAC, June 2008.PDF.gifpaper
    15. J. Jeong, S. Paik, and Y. Shin, "Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation,"ASPDAC, Jan. 2008.PDF.gifpaper