Students who want to join the lab

Internship to IMEC in Belgium, 2016.6 - 2016.9 (최수형)    Photo photos
Working on optical-proximity-correction (OPC)
Conference paper accepted to ICCAD, 2016 (정진욱)
"OWARU: free space-aware timing-driven incremental placement"
Conference paper accepted to ISOCC, 2016 (윤기원, 최수형)
"Area efficient neuromorphic circuit based on stochastic computation"
Conference paper accepted to ICCE, 2016 (김상민)
"Synthesis of dual-mode circuits through optimizing transition time constraints"
DAC Richard Newton Young Fellow Award, 2016 (최수형)    Photo photos
The award is named to honor the memory of Dr. A. Richard Newton, a towering figure in EDA, DAC and education.
Conference paper accepted to DAC + SIGDA Ph.D Forum, 2016 (심성보)    Photo photos
"Redundant via insertion for multiple-patterning directed-self-assembly lithography"
SIGDA Ph.D. forum is poster session hosted by ACM SIGDA for Ph.D students to present and discuss their dissertation research with people in the EDA community
Internship to IBM T. J. Watson Research Center in US, 2016.1 - 2016.7 (정우현)    Photo photos
Worked on physical retiming and latch placement & cloning
Journal accepted to IEEE TVLSI, 2016 (심성보, 정우현)
"Lithography defect probability and its application to physical design optimization"
Journal accepted to ACM TODAES, 2016 (김상민)
"Synthesis of dual-mode circuits through library design, gate sizing, and clock tree optimization"
Conference paper invited to ICICDT, 2016 (심성보)    Photo photos
"Placement optimization for MP-DSAL compliant layout"
Conference paper accepted to ICICDT, 2016 (한인학)
"Register grouping for synthesis of clock gating logic"
Conference paper invited to APCCAS, 2016 (심성보, 최수형)
"Machine learning (ML)-based lithograph optimizations"
Conference paper accepted to ISCAS, 2016 (윤기원)    Photo photos
"Crosslink insertion for minimizing OCV clock skew"
Tutorial at ASP-DAC, 2016 (심성보)    Photo photos
"Directed self-assembly lithography (DSAL): mask synthesis and circuit design"
Internship to IBM T. J. Watson Research Center in US, 2015.7 - 2015.12 (정진욱)    Photo photos
Worked on timing driven incremental placement